Datasheet

PIC18F/LF1XK50
DS41350E-page 304 Preliminary  2010 Microchip Technology Inc.
FIGURE 24-2: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F/LF1XK50
Device
Address (from/to) 14K50 13K50
BBSIZ = 1 BBSIZ = 0 BBSIZ = 1 BBSIZ = 0
0000h
01FFh
Boot Block, 2 KW
CPB, WRTB, EBTRB
Boot Block, 1 KW
CPB, WRTB, EBTRB
Boot Block, 1 KW
CPB, WRTB, EBTRB
Boot Block, 0.512 KW
CPB, WRTB, EBTRB
0200h
03FFh
Block 0
1.512 KW
CP0, WRT0, EBTR0
0400h
05FFh
Block 0
3 KW
CP0, WRT0, EBTR0
Block 0
1 KW
CP0, WRT0, EBTR0
0600h
07FFh
0800h
0FFFh
Block 0
2 KW
CP0, WRT0, EBTR0
Block 1
2 KW
CP1, WRT1, EBTR1
Block 1
2 KW
CP1, WRT1, EBTR1
1000h
1FFFh
Block 1
4 KW
CP1, WRT1, EBTR1
Block 1
4 KW
CP1, WRT1, EBTR1
Reads all ‘0’s Reads all ‘0’s
2000h
27FFh
Reads all ‘0’s Reads all ‘0’s
2800h
2FFFh
3000h
37FFh
3800h
3FFFh
4000h
47FFh
4800h
4FFFh
5000h
57FFh
5800h
5FFFh
6000h
67FFh
6800h
6FFFh
7000h
77FFh
7800h
7FFFh
8000h
FFFFh
Note: Refer to the test section for requirements on test memory mapping.