Datasheet

PIC18F/LF1XK50
DS41350E-page 26 Preliminary  2010 Microchip Technology Inc.
TABLE 2-4: LOW SPEED USB CLOCK SETTINGS
TABLE 2-5: FULL-SPEED USB CLOCK SETTINGS
Clock Mode
Clock
Frequency
USBDIV
4x PLL
Enabled
CPUDIV<1:0>
System Clock
Frequency (MHz)
EC High/HS
12 MHz 1
Yes
00 48
01 24
10 16
11 12
No
00 12
01 6
10 4
11 3
6 MHz 0
Yes
00 24
01 12
10 8
11 6
No
00 6
01 3
10 2
11 1.5
Note: The system clock frequency in Table 2-4
only applies if the OSCCON register bits
SCS<1:0> = 00. By changing these bits,
the system clock can operate down to
31 kHz.
Clock Mode Clock Frequency 4x PLL Enabled CPUDIV<1:0>
System Clock Frequency
(MHz)
EC High 48 MHz No
00 48
01 24
10 16
11 12
EC High/HS 12 MHz Yes
00 48
01 24
10 16
11 12
Note: The system clock frequency in the above
table only applies if the OSCCON register
bits SCS<1:0> = 00. By changing these
bits, the system clock can operate down to
31 kHz.