PIC18F/LF1XK50 Data Sheet 20-Pin USB Flash Microcontrollers with nanoWatt XLP Technology 2010 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC18F/LF1XK50 20-Pin USB Flash Microcontrollers with nanoWatt XLP Technology Universal Serial Bus Features: Extreme Low-Power Management PIC18LF1XK50 with nanoWatt XLP: • USB V2.0 Compliant SIE • Full Speed (12 Mb/s) and Low Speed (1.
PIC18F/LF1XK50 EUSART - Comp. PIC18F13K50/ PIC18LF13K50 8K 4096 512(3) 256 15 11 1 Y Y 1 2 1/3 Y PIC18F14K50/ PIC18LF14K50 16K 8192 768(3) 256 15 11 1 Y Y 1 2 1/3 Y Program Memory Device Note 1: 2: 3: Data Memory MSSP 10-bit (1) A/D Flash # Single-Word SRAM EEPROM I/O (ch)(2) (bytes) Instructions (bytes) (bytes) ECCP (PWM) SPI Master I2C™ Timers USB 8/16-bit One pin is input only.
PIC18F/LF1XK50 Basic RA0 IOCA0 D+ PGD RA1 IOCA1 D- 4 RA3(1) IOCA3 Y MCLR/VPP 3 RA4 2 RA5 13 RB4 AN10 12 RB5 AN11 11 RB6 10 RB7 16 RC0 AN4 C12IN+ VREF+ INT0 15 RC1 AN5 C12IN1- VREF- INT1 14 RC2 AN6 C12IN2- CVREF 7 RC3 AN7 C12IN3- P1C 6 RC4 C12OUT P1B 5 RC5 8 RC6 AN8 SS T13CKI/T1OSCI 9 RC7 AN9 SDO T1OSCO I/O 19 18 Pin USB Pull-up Interrupts Timers MSSP EUSART ECCP Reference Comparator PIC18F/LF1XK50 PIN SUMMARY Analog TABLE 1: AN3
PIC18F/LF1XK50 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 15 3.0 Memory Organization .......................................................................................
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PIC18F/LF1XK50 NOTES: DS41350E-page 8 Preliminary 2010 Microchip Technology Inc.
PIC18F1XK50/PIC18LF1XK50 1.0 DEVICE OVERVIEW 1.1.2 This document contains device specific information for the following devices: • PIC18F13K50 • PIC18F14K50 • PIC18LF13K50 • PIC18LF14K50 This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price – with the addition of high-endurance, Flash program memory.
PIC18F1XK50/PIC18LF1XK50 1.2 Other Special Features 1.3 • Memory Endurance: The Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 1K for program memory and 100K for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. • Self-programmability: These devices can write to their own program memory spaces under internal software control.
PIC18F1XK50/PIC18LF1XK50 TABLE 1-1: DEVICE FEATURES FOR THE PIC18F/LF1XK50 (20-PIN DEVICES) Features LDO Regulator Program Memory (Bytes) PIC18F13K50 PIC18LF13K50 PIC18F14K50 PIC18LF14K50 Yes No Yes No 8K 16K Program Memory (Instructions) 4096 8192 Data Memory (Bytes) 512 768 Operating Frequency DC – 48 MHz Interrupt Sources 30 I/O Ports Ports A, B, C Timers 4 Enhanced Capture/ Compare/PWM Modules Serial Communications 1 MSSP, Enhanced USART, USB 10-Bit Analog-to-Digital Module
PIC18F1XK50/PIC18LF1XK50 FIGURE 1-1: PIC18F/LF1XK50 BLOCK DIAGRAM Data Bus<8> Table Pointer<21> Data Latch 8 8 inc/dec logic PCLATU PCLATH 21 PORTA Data Memory (512/768 bytes) Address Latch 20 PCU PCH PCL Program Counter RA0 RA1 RA3 RA4 RA5 12 Data Address<12> 31-Level Stack 4 BSR Address Latch STKPTR Program Memory 12 FSR0 FSR1 FSR2 Data Latch 4 Access Bank 12 PORTB 8 inc/dec logic Table Latch RB4 RB5 RB6 RB7 Address Decode ROM Latch Instruction Bus <16> IR 8 Instruction Decode and
PIC18F1XK50/PIC18LF1XK50 TABLE 1-2: PIC18F/LF1XK50 PINOUT I/O DESCRIPTIONS Pin Name Pin Pin Number Type RA0/D+/PGD RA0 D+ PGD 19 RA1/D-/PGC RA1 DPGC 18 RA3/MCLR/VPP RA3 MCLR VPP 4 RA4/AN3/OSC2/CLKOUT RA4 AN3 OSC2 3 CLKOUT RA5/OSC1/CLKIN RA5 OSC1 Description I I/O I/O TTL XCVR ST Digital input USB differential plus line (input/output) ICSP™ programming data pin I I/O I/O TTL XCVR ST Digital input USB differential minus line (input/output) ICSP™ programming clock pin I I P ST ST — I/O I
PIC18F1XK50/PIC18LF1XK50 TABLE 1-2: PIC18F/LF1XK50 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Pin Number Type RC0/AN4/C12IN+/INT0/VREF+ RC0 AN4 C12IN+ INT0 VREF+ 16 RC1/AN5/C12IN-/INT1/VREFRC1 AN5 C12ININT1 VREF- 15 RC2/AN6/P1D/C12IN2-/CVREF/INT2 RC2 AN6 P1D C12IN2CVREF INT2 14 RC3/AN7/P1C/C12IN3-/PGM RC3 AN7 P1C C12IN3PGM 7 RC4/P1B/C12OUT/SRQ RC4 P1B C12OUT SRQ 6 RC5/CCP1/P1A/T0CKI RC5 CCP1 P1A T0CKI 5 RC6/AN8/SS/T13CKI/T1OSCI RC6 AN8 SS T13CKI T1OSCI 8 RC7/AN9/SDO/T1OSCO RC7 AN9 SD
PIC18F/LF1XK50 2.0 OSCILLATOR MODULE 2.2 2.1 Overview The SCS bits of the OSCCON register select between the following clock sources: The oscillator module has a variety of clock sources and features that allow it to be used in a wide range of applications, maximizing performance and minimizing power consumption. Figure 2-1 illustrates a block diagram of the oscillator module.
PIC18F/LF1XK50 PIC® MCU CLOCK SOURCE BLOCK DIAGRAM FIGURE 2-1: PIC18F/LF1XK50 2 Low Speed USB 1 0 Primary Oscillator High Speed USB USBDIV OSC1 Sleep IDLEN PCLKEN PRI_SD OSC2 4 x PLL 1 0 CPU Divider Sleep 00 FOSC<3:0> Peripherals PLLEN SPLLEN MUX 1x IRCF<2:0> 16 MHz 31 kHz LFINTOSC 8 MHz 01 CPU Sleep 111 110 4 MHz 2 MHz 1 MHz 500 kHz 101 100 011 MUX Postscaler Internal Oscillator Block 16 MHz HFINTOSC System Clock Clock Control FOSC<3:0> SCS<1:0> 010 250 kHz 001 1 31 k
PIC18F/LF1XK50 2.3.1 PRIMARY EXTERNAL OSCILLATOR SHUT-DOWN FIGURE 2-2: The Primary External Oscillator can be enabled or disabled via software. To enable software control of the Primary External Oscillator, the PCLKEN bit of the CONFIG1H Configuration register must be set. With the PCLKEN bit set, the Primary External Oscillator is controlled by the PRI_SD bit of the OSCCON2 register. The Primary External Oscillator will be enabled when the PRI_SD bit is set, and disabled when the PRI_SD bit is clear.
PIC18F/LF1XK50 FIGURE 2-3: CERAMIC RESONATOR OPERATION (XT OR HS MODE) • Input threshold voltage variation • Component tolerances • Variation in capacitance due to packaging PIC® MCU OSC1/CLKIN C1 To Internal Logic RP(3) RF(2) C2 Ceramic RS(1) Resonator Sleep OSC2/CLKOUT Note 1: A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M.
PIC18F/LF1XK50 2.5 Internal Oscillator The internal oscillator module contains two independent oscillators which are: • LFINTOSC: Low-Frequency Internal Oscillator • HFINTOSC: High-Frequency Internal Oscillator When operating with either oscillator, OSC1 will be an I/O and OSC2 will be either an I/O or CLKOUT. The CLKOUT function is selected by the FOSC bits of the CONFIG1H Configuration register.
PIC18F/LF1XK50 2.6 Oscillator Control The Oscillator Control (OSCCON) (Register 2-1) and the Oscillator Control 2 (OSCCON2) (Register 2-2) registers control the system clock and frequency selection options.
PIC18F/LF1XK50 REGISTER 2-2: OSCCON2: OSCILLATOR CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R-x — — — — — PRI_SD HFIOFL LFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2 PRI_SD: Primary Oscillator Drive Circuit shutdown bit 1 = Oscillator drive circuit on 0 = Oscillator drive circuit o
PIC18F/LF1XK50 2.6.1 OSCTUNE REGISTER The HFINTOSC is factory calibrated, but can be adjusted in software by writing to the TUN<5:0> bits of the OSCTUNE register (Register 2-3). The default value of the TUN<5:0> is ‘000000’. The value is a 6-bit two’s complement number. When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new frequency. Code execution continues during this shift, while giving no indication that the shift has occurred.
PIC18F/LF1XK50 2.7 Oscillator Start-up Timer 2.8 The Primary External Oscillator, when configured for LP, XT or HS modes, incorporates an Oscillator Start-up Timer (OST). The OST ensures that the oscillator starts and provides a stable clock to the oscillator module. The OST times out when 1024 oscillations on OSC1 have occurred. During the OST period, with the system clock set to the Primary External Oscillator, the program counter does not increment suspending program execution.
PIC18F/LF1XK50 TABLE 2-2: EXAMPLES OF DELAYS DUE TO CLOCK SWITCHING Switch From Switch To Oscillator Delay Sleep/POR LFINTOSC HFINTOSC Oscillator Warm-up Delay (TWARM) Sleep/POR LP, XT, HS 1024 clock cycles Sleep/POR EC, RC 8 clock cycles 2.9 4x Phase Lock Loop Frequency Multiplier Note: A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower-frequency external oscillator or to operate at 32 MHz with the HFINTOSC.
PIC18F/LF1XK50 2.11 USB Operation The USB module is designed to operate in two different modes: • Low Speed • Full Speed Because of timing requirements imposed by the USB specifications, the Primary External Oscillator is required for the USB module. The FOSC bits of the CONFIG1H Configuration register must be set to either External Clock (EC) High-power or HS mode with a clock frequency of 6, 12 or 48 MHz. 2.11.
PIC18F/LF1XK50 TABLE 2-4: Clock Mode LOW SPEED USB CLOCK SETTINGS Clock Frequency 4x PLL Enabled USBDIV CPUDIV<1:0> System Clock Frequency (MHz) 00 48 01 24 10 16 11 12 00 12 01 6 10 4 11 3 00 24 01 12 10 8 11 6 00 6 01 3 10 2 11 1.5 Yes 12 MHz 1 No EC High/HS Yes 6 MHz 0 No Note: The system clock frequency in Table 2-4 only applies if the OSCCON register bits SCS<1:0> = 00. By changing these bits, the system clock can operate down to 31 kHz.
PIC18F/LF1XK50 2.12 FIGURE 2-6: Two-Speed Start-up Mode Two-Speed Start-up mode provides additional power savings by minimizing the latency between external Oscillator Start-up Timer (OST) and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the OST period, which can reduce the overall power consumption of the device.
PIC18F/LF1XK50 2.13.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared by either one of the following: • Any Reset • By toggling the SCS1 bit of the OSCCON register Both of these conditions restart the OST. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared and the device automatically switches over to the external clock source.
PIC18F1XK50/PIC18LF1XK50 3.0 MEMORY ORGANIZATION 3.1 There are three types of memory in PIC18 Enhanced microcontroller devices: • Program Memory • Data RAM • Data EEPROM Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘0’s (a NOP instruction).
PIC18F1XK50/PIC18LF1XK50 3.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU.
PIC18F1XK50/PIC18LF1XK50 3.1.2.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs. The STKPTR register (Register 3-1) contains the Stack Pointer value, the STKFUL (stack full) bit and the STKUNF (stack underflow) bits.
PIC18F1XK50/PIC18LF1XK50 3.1.2.4 Stack Full and Underflow Resets 3.1.4 Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit but not cause a device Reset.
PIC18F1XK50/PIC18LF1XK50 3.2 3.2.2 PIC18 Instruction Cycle 3.2.1 An “Instruction Cycle” consists of four Q cycles: Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.
PIC18F1XK50/PIC18LF1XK50 3.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as either two bytes or four bytes in program memory. The Least Significant Byte (LSB) of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSb will always read ‘0’ (see Section 3.1.1 “Program Counter”).
PIC18F1XK50/PIC18LF1XK50 3.3 Note: 3.3.2 Data Memory Organization The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 3.5 “Data Memory and the Extended Instruction Set” for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each.
PIC18F1XK50/PIC18LF1XK50 FIGURE 3-5: DATA MEMORY MAP FOR PIC18F13K50/PIC18LF13K50 DEVICES BSR<3:0> = 0000 00h Access RAM FFh 00h GPR Bank 0 = 0001 Bank 1 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 FFh 00h Bank 2 Bank 3 Bank 4 Bank 5 FFh 00h Unused Read 00h GPR (DPRAM) 000h 05Fh 060h 0FFh 100h 1FFh 200h 2FFh 300h FFh 00h 3FFh 400h FFh 00h 4FFh 500h FFh 00h 5FFh 600h FFh 00h 6FFh 700h The BSR is ignored and the Access Bank is
PIC18F1XK50/PIC18LF1XK50 FIGURE 3-6: DATA MEMORY MAP FOR PIC18F14K50/PIC18LF14K50 DEVICES BSR<3:0> = 0000 00h Access RAM FFh 00h GPR Bank 0 = 0001 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 FFh 00h Bank 2 Bank 3 Bank 4 Bank 5 FFh 00h GPR (DPRAM) 1FFh 200h 2FFh 300h FFh 00h 3FFh 400h FFh 00h 4FFh 500h FFh 00h 5FFh 600h FFh 00h 6FFh 700h The BSR is ignored and the Access Bank is used.
PIC18F1XK50/PIC18LF1XK50 FIGURE 3-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) 0 Data Memory BSR(1) 7 0 0 0 0 0 0 1 1 000h 00h Bank 0 100h Bank 1 Bank Select(2) FFh 00h From Opcode(2) 7 1 1 1 1 1 1 0 1 1 FFh 00h 200h Bank 2 300h FFh 00h Bank 3 through Bank 13 FFh 00h E00h Bank 14 F00h Bank 15 FFFh Note 1: 2: FFh 00h FFh The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank.
PIC18F1XK50/PIC18LF1XK50 3.3.3 ACCESS BANK 3.3.4 While the use of the BSR with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. Otherwise, data may be read from or written to the wrong location. This can be disastrous if a GPR is the intended target of an operation, but an SFR is written to instead.
PIC18F1XK50/PIC18LF1XK50 TABLE 3-1: Address SPECIAL FUNCTION REGISTER MAP FOR PIC18F/LF1XK50 DEVICES Name Address Name Address Name Address Name (2) Address Name FFFh TOSU FD7h TMR0H FAFh SPBRG F87h — F5Fh UEIR FFEh TOSH FD6h TMR0L FAEh RCREG F86h —(2) F5Eh UFRMH FFDh TOSL FD5h T0CON FADh TXREG F85h —(2) F5Dh UFRML (2) F5Ch UADDR (2) FFCh STKPTR FD4h FACh TXSTA F84h — FFBh PCLATU FD3h OSCCON — FABh RCSTA F83h —(2) F5Bh UEIE FFAh PCLATH FD2h OSC
PIC18F1XK50/PIC18LF1XK50 TABLE 3-2: File Name TOSU REGISTER FILE SUMMARY (PIC18F/LF1XK50) Bit 7 Bit 6 Bit 5 — — — TOSH Top-of-Stack, High Byte (TOS<15:8>) TOSL Top-of-Stack, Low Byte (TOS<7:0>) STKPTR STKFUL STKUNF — PCLATU — — — PCLATH Holding Register for PC<15:8> PCL PC, Low Byte (PC<7:0>) TBLPTRU TBLPTRH — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Top-of-Stack Upper Byte (TOS<20:16>) Value on POR, BOR Details on page: ---0 0000 285, 30 0000 0000 285, 30 0000 0000 285, 30 SP4 SP3
PIC18F1XK50/PIC18LF1XK50 TABLE 3-2: File Name REGISTER FILE SUMMARY (PIC18F/LF1XK50) (CONTINUED) Bit 7 Bit 6 TMR0H Timer0 Register, High Byte TMR0L Timer0 Register, Low Byte T0CON Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: 0000 0000 286, 103 xxxx xxxx 286, 103 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOSF SCS1 SCS0 0011 qq00 286, 20 OSCCON2 — — — — — PRI_SD HFIOFL LFIOFS ---- -10x 286, 21 — —
PIC18F1XK50/PIC18LF1XK50 TABLE 3-2: File Name REGISTER FILE SUMMARY (PIC18F/LF1XK50) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: SPBRGH EUSART Baud Rate Generator Register, High Byte 0000 0000 287, 181 SPBRG EUSART Baud Rate Generator Register, Low Byte 0000 0000 287, 181 RCREG EUSART Receive Register 0000 0000 287, 182 TXREG EUSART Transmit Register 0000 0000 287, 181 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 2
PIC18F1XK50/PIC18LF1XK50 TABLE 3-2: File Name REGISTER FILE SUMMARY (PIC18F/LF1XK50) (CONTINUED) Value on POR, BOR Details on page: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 USTAT — ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI — UIR — SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF -000 0000 289, 266 UTEYE — — UPUEN — FSEN PPB1 PPB0 0--0 -000 289, 254 — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE -000 0000 289, 268 — UCFG UIE -xxx xxx- 289, 256 BTSEF — BTOE
PIC18F1XK50/PIC18LF1XK50 3.3.6 STATUS REGISTER The STATUS register, shown in Register 3-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the STATUS register is updated according to the instruction performed.
PIC18F1XK50/PIC18LF1XK50 3.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 3.5 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way – through the program counter – information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed.
PIC18F1XK50/PIC18LF1XK50 3.4.3.1 FSR Registers and the INDF Operand 3.4.3.2 At the core of indirect addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. Each FSR pair holds a 12-bit value, therefore the four upper bits of the FSRnH register are not used. The 12-bit FSR value can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations.
PIC18F1XK50/PIC18LF1XK50 Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair; that is, rollovers of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). The PLUSW register can be used to implement a form of indexed addressing in the data memory space.
PIC18F1XK50/PIC18LF1XK50 FIGURE 3-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When ‘a’ = 0 and f 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and 0FFh. This is the same as locations F60h to FFFh (Bank 15) of data memory. Locations below 60h are not available in this addressing mode.
PIC18F1XK50/PIC18LF1XK50 3.5.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the first 96 locations of Access RAM (00h to 5Fh) are mapped. Rather than containing just the contents of the bottom section of Bank 0, this mode maps the contents from a user defined “window” that can be located anywhere in the data memory space.
PIC18F1XK50/PIC18LF1XK50 4.0 FLASH PROGRAM MEMORY 4.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: A read from program memory is executed one byte at a time.
PIC18F1XK50/PIC18LF1XK50 FIGURE 4-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Table Pointer(1) TBLPTRU TBLPTRH Holding Registers Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: During table writes the Table Pointer does not point directly to Program Memory. The LSBs of TBLPRTL actually point to an address within the write block holding registers. The MSBs of the Table Pointer determine where the write block will eventually be written.
PIC18F1XK50/PIC18LF1XK50 REGISTER 4-1: EECON1: DATA EEPROM CONTROL 1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘0’ = Bit is cleared ‘1’ = Bit is set x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPR
PIC18F1XK50/PIC18LF1XK50 4.2.2 TABLAT – TABLE LATCH REGISTER 4.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 4.2.3 TABLE POINTER BOUNDARIES TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory directly into the TABLAT register.
PIC18F1XK50/PIC18LF1XK50 4.3 Reading the Flash Program Memory The TBLRD instruction retrieves data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 4-4 shows the interface between the internal program memory and the TABLAT. TBLPTR points to a byte address in program space.
PIC18F1XK50/PIC18LF1XK50 4.4 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP™ control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the Microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased.
PIC18F1XK50/PIC18LF1XK50 4.5 Writing to Flash Program Memory The programming block size is 8 or 16 bytes, depending on the device (See Table 4-1). Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are only as many holding registers as there are bytes in a write block (See Table 4-1).
PIC18F1XK50/PIC18LF1XK50 EXAMPLE 4-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'64’ COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; number of bytes in erase block TBLRD*+ MOVF MOVWF DECFSZ BRA TABLAT, W POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0
PIC18F1XK50/PIC18LF1XK50 EXAMPLE 4-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) DECFSZ BRA COUNTER WRITE_WORD_TO_HREGS ; loop until holding registers are full BSF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF DCFSZ BRA BSF BCF EECON1, EEPGD EECON1, CFGS EECON1, WREN INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR COUNTER2 WRITE_BYTE_TO_HREGS INTCON, GIE EECON1, WREN ; ; ; ; PROGRAM_MEMORY Required Sequence 4.5.
PIC18F1XK50/PIC18LF1XK50 NOTES: DS41350E-page 60 Preliminary 2010 Microchip Technology Inc.
PIC18F/LF1XK50 5.0 DATA EEPROM MEMORY The data EEPROM is a nonvolatile memory array, separate from the data RAM and program memory, which is used for long-term storage of program data. It is not directly mapped in either the register file or program memory space but is indirectly addressed through the Special Function Registers (SFRs). The EEPROM is readable and writable during normal operation over the entire VDD range.
PIC18F/LF1XK50 REGISTER 5-1: EECON1: DATA EEPROM CONTROL 1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘0’ = Bit is cleared ‘1’ = Bit is set x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory
PIC18F/LF1XK50 5.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit of the EECON1 register and then set control bit, RD. The data is available on the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation). The basic process is shown in Example 5-1.
PIC18F/LF1XK50 5.6 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in Configuration Words. External read and write operations are disabled if code protection is enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect Configuration bit. Refer to Section 24.0 “Special Features of the CPU” for additional information. 5.
PIC18F/LF1XK50 6.0 8 x 8 HARDWARE MULTIPLIER 6.1 Introduction EXAMPLE 6-1: MOVF MULWF All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS register.
PIC18F/LF1XK50 Example 6-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 6-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES<3:0>).
PIC18F/LF1XK50 7.0 INTERRUPTS 7.2 The PIC18F/LF1XK50 devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 0008h and the low priority interrupt vector is at 0018h. A high priority interrupt event will interrupt a low priority interrupt that may be in progress. There are ten registers which are used to control interrupt operation.
PIC18F/LF1XK50 instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bits or the global interrupt enable bit. Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior. DS41350E-page 68 Preliminary 2010 Microchip Technology Inc.
PIC18F/LF1XK50 FIGURE 7-1: PIC18 INTERRUPT LOGIC TMR0IF TMR0IE TMR0IP RABIF RABIE RABIP INT0IF INT0IE Wake-up if in Idle or Sleep modes (1) Interrupt to CPU Vector to Location 0008h INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP SSPIF SSPIE SSPIP GIEH/GIE ADIF ADIE ADIP IPEN IPEN GIEL/PEIE RCIF RCIE RCIP IPEN Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation SSPIF SSPIE SSPIP Interrupt to CPU Vector to Location 0018h TMR0IF TMR0IE TMR0IP ADIF ADIE
PIC18F/LF1XK50 7.4 INTCON Registers Note: The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits. REGISTER 7-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
PIC18F/LF1XK50 REGISTER 7-2: INTCON2: INTERRUPT CONTROL 2 REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RABPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RABIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RABPU: PORTA and PORTB Pull-up Enable bit 1 = All PORTA and PORTB pull-ups are disabled 0 = PORTA and PORTB pull-ups are enabled provided that the pin is an
PIC18F/LF1XK50 REGISTER 7-3: INTCON3: INTERRUPT CONTROL 3 REGISTER R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Lo
PIC18F/LF1XK50 7.5 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Request Flag registers (PIR1 and PIR2). Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE of the INTCON register.
PIC18F/LF1XK50 REGISTER 7-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 OSCFIF C1IF C2IF EEIF BCLIF USBIF TMR3IF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to HFINTOSC (must be cleared by software) 0 =
PIC18F/LF1XK50 7.6 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1 and PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
PIC18F/LF1XK50 REGISTER 7-7: PIE2: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 OSCFIE C1IE C2IE EEIE BCLIE USBIE TMR3IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 C1IE: Comparator C1 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 C2IE: Compar
PIC18F/LF1XK50 7.7 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1 and IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
PIC18F/LF1XK50 REGISTER 7-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 OSCFIP C1IP C2IP EEIP BCLIP USBIP TMR3IP — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 C1IP: Comparator C1 Interrupt Priority bit 1 = High priority 0 = Low priority
PIC18F/LF1XK50 7.8 RCON Register The RCON register contains flag bits which are used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the IPEN bit which enables interrupt priorities. The operation of the SBOREN bit and the Reset flag bits is discussed in more detail in Section 23.1 “RCON Register”.
PIC18F/LF1XK50 7.9 INTn Pin Interrupts 7.10 TMR0 Interrupt External interrupts on the RC0/INT0, RC1/INT1 and RC2/INT2 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RCx/INTx pin, the corresponding flag bit, INTxF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxE.
PIC18F1XK50/PIC18LF1XK50 8.0 LOW DROPOUT (LDO) VOLTAGE REGULATOR The PIC18F1XK50 devices differ from the PIC18LF1XK50 devices due to an internal Low Dropout (LDO) voltage regulator. The PIC18F1XK50 contain an internal LDO, while the PIC18LF1XK50 do not. The lithography of the die allows a maximum operating voltage of the nominal 3.6V on the internal digital logic. In order to continue to support 5.0V designs, a LDO voltage regulator is integrated on the die.
PIC18F1XK50/PIC18LF1XK50 NOTES: DS41350E-page 82 Preliminary 2010 Microchip Technology Inc.
PIC18F/LF1XK50 9.0 I/O PORTS 9.1 There are up to three ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation.
PIC18F/LF1XK50 Note 1: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RABIF interrupt flag may not get set. Furthermore, since a read or write on a port affects all bits of that port, care must be taken when using multiple pins in Interrupt-on-change mode. Changes on one pin may not be seen while servicing changes on another pin.
PIC18F/LF1XK50 REGISTER 9-1: PORTA: PORTA REGISTER U-0 U-0 R/W-x R/W-x R-x U-0 R/W-x R/W-x — — RA5 RA4 RA3 — RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-3 RA<5:3>: PORTA I/O Pin bit(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 2 Unimplemented: Read as ‘0’ bit 1-0 RA<1:0>: PORTA I/O Pin bit 1 = Port pin is > VIH 0 = Port p
PIC18F/LF1XK50 REGISTER 9-3: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-1 R/W-1 RW-1 U-0 U-0 U-0 — — WPUA5 WPUA4 WPUA3 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-3 WPUA<5:3>: Weak Pull-up Enable bit 1 = Pull-up enabled 0 = Pull-up disabled bit 2 Unimplemented: Read as ‘0’ bit 1-0 WPUA<1:0>: Weak Pull-up Enable bit 1 = Pull-up
PIC18F/LF1XK50 TABLE 9-1: Pin RA0/IOCA0/D+/ PGD PORTA I/O SUMMARY Function TRIS Setting I/O I/O Type RA0 —(1) I TTL PORTA<0> data input; disabled when USB enabled. (1) I TTL Interrupt-on-pin change; disabled when USB enabled. —(1) I XCVR USB bus differential plus line input (internal transceiver). —(1) O XCVR USB bus differential plus line output (internal transceiver).
PIC18F/LF1XK50 TABLE 9-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Reset Values on page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTA — — RA5(1) RA4(1) RA3(2) — RA1(3) RA0(3) 288 LATA — — LATA5(1) LATA4(1) — — — — 288 TRISA — — TRISA5(1) TRISA4(1) — — — — 288 ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 — — — 288 — — — — — SLRC SLRB SLRA SLRCON (2) IOCA — — IOCA5 IOCA4 WPUA — — WPUA5 WPUA4 UCON — PPBRST SE0 PKTDIS USBEN TMR0IE INT0
PIC18F/LF1XK50 9.2 PORTB, TRISB and LATB Registers holding the last read value is not affected by a MCLR nor Brown-out Reset. After either one of these Resets, the RABIF flag will continue to be set if a mismatch is present. PORTB is an 4-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., disable the output driver). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e.
PIC18F/LF1XK50 REGISTER 9-6: PORTB: PORTB REGISTER R/W-x R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0 RB7 RB6 RB5 RB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 RB<7:4>: PORTB I/O Pin bit 1 = Port pin is >VIH 0 = Port pin is
PIC18F/LF1XK50 REGISTER 9-8: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0 WPUB7 WPUB6 WPUB5 WPUB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 WPUB<7:4>: Weak Pull-up Enable bit 1 = Pull-up enabled 0 = Pull-up disabled bit 3-0 Unimplemented: Read as ‘0’ REGISTER 9-9: x = Bit is unknown IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER R/W-0
PIC18F/LF1XK50 TABLE 9-3: PORTB I/O SUMMARY Pin Function TRIS Setting I/O I/O Type RB4/IOCB4/AN10/ SDI/SDA RB4 0 O DIG LATB<4> data output; not affected by analog input. PORTB<4> data input; Programmable weak pull-up. RB5/IOCB5/AN11/ RX/DT RB6/IOCB6/SCK/ SCL 1 I TTL IOCB4 1 I TTL Interrupt-on-pin change. AN10 1 I ANA ADC input channel 10. SDI 1 I ST SPI data input (MSSP module). SDA 1 I DIG I2C™ data output (MSSP module); takes priority over port data.
PIC18F/LF1XK50 TABLE 9-4: Name PORTB LATB SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page RB7 RB6 RB5 RB4 — — — — 288 LATB7 LATB6 LATB5 LATB4 — — — — 288 TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 288 WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 288 IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — — SLRC SLRB SLRA TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285 — TMR0IP — RABIP 285 ANS11 ANS10 A
PIC18F/LF1XK50 9.3 PORTC, TRISC and LATC Registers All the pins on PORTC are implemented with Schmitt Trigger input buffer. Each pin is individually configurable as an input or output. PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., disable the output driver). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e.
PIC18F/LF1XK50 REGISTER 9-13: LATC: PORTC DATA LATCH REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown LATC<7:0>: RB<7:0> Port I/O Output Latch Register bits 2010 Microchip Technology Inc.
PIC18F/LF1XK50 TABLE 9-14: Pin RC0/AN4/ C12IN+/VREF+/ INT0 RC1/AN5/ C12IN1-/VREF-/ INT1 RC2/AN6/ C12IN2-/CVREF/ P1D/INT2 RC3/AN7/ C12IN3-/P1C/ PGM RC4/C12OUT/ P1B Legend: PORTC I/O SUMMARY Function TRIS Setting I/O I/O Type RC0 0 O DIG 1 I ST AN4 1 I ANA A/D input channel 4. C12IN+ 1 I ANA Comparators C1 and C2 non-inverting input. Analog select is shared with ADC. VREF+ 1 I ANA ADC and comparator voltage reference high input. Description LATC<0> data output.
PIC18F/LF1XK50 TABLE 9-14: PORTC I/O SUMMARY (CONTINUED) Pin RC5/CCP1/P1A/ T0CKI Function TRIS Setting I/O I/O Type RC5 0 O DIG CCP1 RC6/AN8/SS/ T13CKI/T1OSCI RC7/AN9/SDO/ T1OSCO LATC<5> data output. 1 I ST PORTC<5> data input. 0 O DIG ECCP1 compare or PWM output; takes priority over port data. 1 I ST ECCP1 capture input. P1A 0 0 DIG ECCP1 Enhanced PWM output, channel A. May be configured for tri-state during Enhanced PWM shutdown events.
PIC18F/LF1XK50 9.4 Port Analog Control Some port pins are multiplexed with analog functions such as the Analog-to-Digital Converter and comparators. When these I/O pins are to be used as analog inputs it is necessary to disable the digital input buffer to avoid excessive current caused by improper biasing of the digital input. Individual control of the digital input buffers on pins which share analog functions is provided by the ANSEL and ANSELH registers.
PIC18F/LF1XK50 REGISTER 9-16: ANSELH: ANALOG SELECT REGISTER 2 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 — — — — ANS11 ANS10 ANS9 ANS8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 ANS11: RB5 Analog Select Control bit 1 = Digital input buffer of RB5 is disabled 0 = Digital input buffer of RB5 is enabled bit 2 ANS10: RB4 Analog Select Control
PIC18F/LF1XK50 9.5 Port Slew Rate Control The output slew rate of each port is programmable to select either the standard transition rate or a reduced transition rate of 0.1 times the standard to minimize EMI. The reduced transition time is the default slew rate for all ports.
PIC18F/LF1XK50 10.0 TIMER0 MODULE The T0CON register (Register 10-1) controls all aspects of the module’s operation, including the prescale selection. It is both readable and writable.
PIC18F/LF1XK50 10.1 Timer0 Operation 10.2 Timer0 can operate as either a timer or a counter; the mode is selected with the T0CS bit of the T0CON register. In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 10.3 “Prescaler”). Timer0 incrementing is inhibited for two instruction cycles following a TMR0 register write.
PIC18F/LF1XK50 FIGURE 10-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) FOSC/4 0 0 Sync with Internal Clocks 1 Programmable Prescaler T0CKI pin T0SE T0CS 1 TMR0 High Byte TMR0L 8 Set TMR0IF on Overflow (2 TCY Delay) 3 Read TMR0L T0PS<2:0> Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: 10.3 Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. 10.3.1 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module.
PIC18F/LF1XK50 NOTES: DS41350E-page 104 Preliminary 2010 Microchip Technology Inc.
PIC18F/LF1XK50 11.0 TIMER1 MODULE The Timer1 timer/counter module incorporates the following features: • Software selectable operation as a 16-bit timer or counter • Readable and writable 8-bit registers (TMR1H and TMR1L) • Selectable internal or external clock source and Timer1 oscillator options • Interrupt-on-overflow • Reset on CCP Special Event Trigger • Device clock status flag (T1RUN) REGISTER 11-1: A simplified block diagram of the Timer1 module is shown in Figure 11-1.
PIC18F/LF1XK50 11.1 Timer1 Operation instruction cycle (FOSC/4). When the bit is set, Timer1 increments on every rising edge of either the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer1 can operate in one of the following modes: • Timer • Synchronous Counter • Asynchronous Counter When the Timer1 oscillator is enabled, the digital circuitry associated with the T1OSI and T1OSO pins is disabled. This means the values of TRISC<1:0> are ignored and the pins are read as ‘0’.
PIC18F/LF1XK50 11.2 TABLE 11-1: Timer1 16-Bit Read/Write Mode Timer1 can be configured for 16-bit reads and writes (see Figure 11-2). When the RD16 control bit of the T1CON register is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 high byte buffer.
PIC18F/LF1XK50 11.3.2 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS 11.5 The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 11-3, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD.
PIC18F/LF1XK50 11.6 Using Timer1 as a Real-Time Clock Adding an external LP oscillator to Timer1 (such as the one described in Section 11.3 “Timer1 Oscillator” above) gives users the option to include RTC functionality to their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time.
PIC18F/LF1XK50 TABLE 11-2: Name INTCON REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288 IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288 TMR1L Timer1 Register, Low Byte 286 TMR1H Timer1 Register, High Byte 286 T1C
PIC18F/LF1XK50 12.0 TIMER2 MODULE 12.
PIC18F/LF1XK50 12.2 Timer2 Interrupt 12.3 Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2-to-PR2 match) provides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF of the PIR1 register. The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE of the PIE1 register.
PIC18F/LF1XK50 13.0 TIMER3 MODULE The Timer3 module timer/counter incorporates these features: • Software selectable operation as a 16-bit timer or counter • Readable and writable 8-bit registers (TMR3H and TMR3L) • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt-on-overflow • Module Reset on CCP Special Event Trigger REGISTER 13-1: A simplified block diagram of the Timer3 module is shown in Figure 13-1.
PIC18F/LF1XK50 13.1 Timer3 Operation The operating mode is determined by the clock select bit, TMR3CS of the T3CON register. When TMR3CS is cleared (= 0), Timer3 increments on every internal instruction cycle (FOSC/4). When the bit is set, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled.
PIC18F/LF1XK50 FIGURE 13-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Oscillator Timer1 Clock Input 1 T13CKI/T1OSI 1 T1OSO Synchronize Prescaler 1, 2, 4, 8 FOSC/4 Internal Clock 0 Detect 0 2 (1) T1OSCEN T3CKPS<1:0> T3SYNC TMR3ON Sleep Input Timer3 On/Off TMR3CS CCP1 Special Event Trigger CCP1 Select from T3CON<3> Clear TMR3 Set TMR3IF on Overflow TMR3 High Byte TMR3L 8 Read TMR1L Write TMR1L 8 8 TMR3H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the
PIC18F/LF1XK50 13.5 Resetting Timer3 Using the CCP Special Event Trigger If CCP1 module is configured to use Timer3 and to generate a Special Event Trigger in Compare mode (CCP1M<3:0>), this signal will reset Timer3. It will also start an A/D conversion if the A/D module is enabled (see Section 17.2.8 “Special Event Trigger” for more information). The module must be configured as either a timer or synchronous counter to take advantage of this feature.
PIC18F/LF1XK50 14.0 ENHANCED CAPTURE/COMPARE/PWM (ECCP) MODULE CCP1 is implemented as a standard CCP module with enhanced PWM capabilities. These include: PIC18F/LF1XK50 devices have one ECCP (Capture/Compare/PWM) module. The module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register.
PIC18F/LF1XK50 In addition to the expanded range of modes available through the CCP1CON register and ECCP1AS register, the ECCP module has two additional registers associated with Enhanced PWM operation and auto-shutdown features. They are: • PWM1CON (Dead-band delay) • PSTRCON (output steering) 14.1 ECCP Outputs and Configuration The enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode.
PIC18F/LF1XK50 14.2 Capture Mode be used with each CCP module is selected in the T3CON register (see Section 14.1.1 “CCP Module and Timer Resources”). In Capture mode, the CCPR1H:CCPR1L register pair captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on the corresponding CCP1 pin. An event is defined as one of the following: • • • • 14.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated.
PIC18F/LF1XK50 14.3 14.3.2 Compare Mode TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPR1 register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCP1 pin can be: Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation will not work reliably. • • • • 14.3.
PIC18F/LF1XK50 14.4 PWM (Enhanced Mode) The PWM outputs are multiplexed with I/O pins and are designated P1A, P1B, P1C and P1D. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately. The Enhanced PWM Mode can generate a PWM signal on up to four different output pins with up to 10-bits of resolution. It can do this through four different PWM output modes: • • • • Table 14-1 shows the pin assignments for each Enhanced PWM mode.
PIC18F/LF1XK50 FIGURE 14-4: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) P1M<1:0> Signal PR2+1 Pulse Width 0 Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPR1L<
PIC18F/LF1XK50 FIGURE 14-5: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) Signal P1M<1:0> PR2+1 Pulse Width 0 Period 00 (Single Output) P1A Modulated P1A Modulated Delay(1) 10 (Half-Bridge) Delay(1) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPR1L<7:0>:CCP1
PIC18F/LF1XK50 14.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCP1/P1A pin, while the complementary PWM output signal is output on the P1B pin (see Figure 14-6). This mode can be used for Half-Bridge applications, as shown in Figure 14-7, or for Full-Bridge applications, where four power switches are being modulated with two PWM signals.
PIC18F/LF1XK50 14.4.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of Full-Bridge application is shown in Figure 14-8. In the Forward mode, pin CCP1/P1A is driven to its active state, pin P1D is modulated, while P1B and P1C will be driven to their inactive state as shown in Figure 14-9. In the Reverse mode, P1C is driven to its active state, pin P1B is modulated, while P1A and P1D will be driven to their inactive state as shown Figure 14-9.
PIC18F/LF1XK50 FIGURE 14-9: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A (2) Pulse Width P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Pulse Width P1A(2) P1B(2) P1C(2) P1D(2) (1) Note 1: 2: (1) At this time, the TMR2 register is equal to the PR2 register. Output signal is shown as active-high. DS41350E-page 126 Preliminary 2010 Microchip Technology Inc.
PIC18F/LF1XK50 14.4.2.1 Direction Change in Full-Bridge Mode In the Full-Bridge mode, the P1M1 bit in the CCP1CON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. A direction change is initiated in software by changing the P1M1 bit of the CCP1CON register.
PIC18F/LF1XK50 FIGURE 14-11: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A P1B PW P1C P1D PW TON External Switch C TOFF External Switch D Potential Shoot-Through Current Note 1: 14.4.3 T = TOFF – TON All signals are shown as active-high. 2: TON is the turn on delay of power switch QC and its driver. 3: TOFF is the turn off delay of power switch QD and its driver.
PIC18F/LF1XK50 14.4.4 ENHANCED PWM AUTO-SHUTDOWN MODE The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application. The auto-shutdown sources are selected using the ECCPAS<2:0> bits of the ECCPAS register.
PIC18F/LF1XK50 Note 1: The auto-shutdown condition is a level-based signal, not an edge-based signal. As long as the level is present, the auto-shutdown will persist. 2: Writing to the ECCPASE bit is disabled while an auto-shutdown condition persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart) the PWM signal will always restart at the beginning of the next PWM period.
PIC18F/LF1XK50 14.4.5 AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PRSEN bit in the PWM1CON register. If auto-restart is enabled, the ECCPASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the ECCPASE bit will be cleared via hardware and normal operation will resume.
PIC18F/LF1XK50 14.4.6 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 14-14: In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off.
PIC18F/LF1XK50 REGISTER 14-3: PWM1CON: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically
PIC18F/LF1XK50 14.4.7 PULSE STEERING MODE In Single Output mode, pulse steering allows any of the PWM pins to be the modulated signal. Additionally, the same PWM signal can be simultaneously available on multiple pins. Once the Single Output mode is selected (CCP1M<3:2> = 11 and P1M<1:0> = 00 of the CCP1CON register), the user firmware can bring out the same PWM signal to one, two, three or four output pins by setting the appropriate STR bits of the PSTRCON register, as shown in Table 14-2.
PIC18F/LF1XK50 FIGURE 14-16: SIMPLIFIED STEERING BLOCK DIAGRAM STRA P1A Signal CCP1M1 1 PORT Data 0 P1A pin STRB CCP1M0 1 PORT Data 0 CCP1M1 1 PORT Data 0 P1C pin TRIS STRD PORT Data P1B pin TRIS STRC CCP1M0 TRIS P1D pin 1 0 TRIS Note 1: Port outputs are configured as shown when the CCP1CON register bits P1M<1:0> = 00 and CCP1M<3:2> = 11. 2: Single PWM output requires setting at least one of the STRx bits. 2010 Microchip Technology Inc.
PIC18F/LF1XK50 14.4.7.1 Steering Synchronization The STRSYNC bit of the PSTRCON register gives the user two selections of when the steering event will happen. When the STRSYNC bit is ‘0’, the steering event will happen at the end of the instruction that writes to the PSTRCON register. In this case, the output signal at the P1 pins may be an incomplete PWM waveform. This operation is useful when the user firmware needs to immediately remove a PWM signal from the pin.
PIC18F/LF1XK50 14.4.8 OPERATION IN POWER-MANAGED MODES In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change. If the ECCP pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state. If Two-Speed Start-ups are enabled, the initial start-up frequency from HFINTOSC and the postscaler may not be stable immediately.
PIC18F/LF1XK50 TABLE 14-3: Name INTCON REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3 Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285 IPEN SBOREN — RI TO PD POR BOR 284 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288 IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288 PIR2 OSCFIF C1IF C2IF EEIF
PIC18F/LF1XK50 15.0 15.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE 15.2 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of SPI are supported. To accomplish communication, typically three pins are used: Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices.
PIC18F/LF1XK50 15.2.1 REGISTERS SSPSR is the shift register used for shifting data in and out. SSPBUF provides indirect access to the SSPSR register. SSPBUF is the buffer register to which data bytes are written, and from which data bytes are read. The MSSP module has four registers for SPI mode operation.
PIC18F/LF1XK50 REGISTER 15-2: SSPCON1: MSSP CONTROL 1 REGISTER (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word (must be
PIC18F/LF1XK50 15.2.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
PIC18F/LF1XK50 15.2.3 ENABLING SPI I/O 15.2.4 To enable the serial port, SSP Enable bit, SSPEN of the SSPCON1 register, must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins.
PIC18F/LF1XK50 15.2.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 15-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
PIC18F/LF1XK50 15.2.6 SLAVE MODE 15.2.7 In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit of the SSPCON1 register.
PIC18F/LF1XK50 FIGURE 15-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 15-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PIC18F/LF1XK50 15.2.8 OPERATION IN POWER-MANAGED MODES Transmit/Receive Shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. In SPI Master mode, module clocks may be operating at a different speed than when in full power mode; in the case of the Sleep mode, all clocks are halted. 15.2.9 In all Idle modes, a clock is provided to the peripherals.
PIC18F/LF1XK50 15.3 I2C Mode 15.3.1 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing.
PIC18F/LF1XK50 REGISTER 15-3: R/W-0 SSPSTAT: MSSP STATUS REGISTER (I2C MODE) R/W-0 SMP CKE R-0 R-0 R-0 D/A (1) (1) P S R-0 R/W (2, 3) R-0 R-0 UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high-
PIC18F/LF1XK50 REGISTER 15-4: SSPCON1: MSSP CONTROL 1 REGISTER (I2C MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid
PIC18F/LF1XK50 REGISTER 15-5: R/W-0 SSPCON2: MSSP CONTROL REGISTER (I2C MODE) R/W-0 GCEN ACKSTAT R/W-0 (2) ACKDT R/W-0 (1) ACKEN R/W-0 (1) RCEN R/W-0 (1) PEN R/W-0 (1) RSEN R/W-0 SEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Generate interrupt when a general call address 0x00 or 00h is received in the S
PIC18F/LF1XK50 15.3.2 OPERATION 15.3.3.1 The MSSP module functions are enabled by setting SSPEN bit of the SSPCON1 register. The SSPCON1 register allows control of the I 2C operation.
PIC18F/LF1XK50 15.3.3.2 Reception 15.3.3.3 When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF bit of the SSPSTAT register is set, or bit SSPOV bit of the SSPCON1 register is set.
DS41350E-page 154 Preliminary CKP 2 A6 3 A5 4 A4 5 A3 6 A2 (CKP does not reset to ‘0’ when SEN = 0) SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 7 A1 8 9 ACK R/W = 0 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared by software SSPBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPBUF is still full. ACK is not sent.
2010 Microchip Technology Inc.
DS41350E-page 156 2 1 Preliminary 4 1 5 0 7 A8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 6 A9 8 9 (CKP does not reset to ‘0’ when SEN = 0) UA (SSPSTAT<1>) SSPOV (SSPCON1<6>) CKP 3 1 Cleared by software BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 ACK R/W = 0 A7 2 4 A4 5 A3 6 A2 8 9 A0 ACK UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address 7 A
2010 Microchip Technology Inc. Preliminary CKP UA BF SSPIF 1 SCL S 1 2 1 4 1 5 0 6 7 A9 A8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 3 1 8 9 ACK R/W = 0 1 3 4 5 Cleared in software 2 7 UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address.
PIC18F/LF1XK50 15.3.3.4 SSP Mask Register This register must be initiated prior to setting SSPM<3:0> bits to select the I2C Slave mode (7-bit or 10-bit address). 2 An SSP Mask (SSPMSK) register is available in I C Slave mode as a mask for the value held in the SSPSR register during an address comparison operation. A zero (‘0’) bit in the SSPMSK register has the effect of making the corresponding bit in the SSPSR register a “don’t care”.
PIC18F/LF1XK50 SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE) REGISTER 15-7: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Master mode: bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC 10-Bit Slave mode — Most significant ad
PIC18F/LF1XK50 15.3.4 CLOCK STRETCHING 15.3.4.3 Both 7-bit and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit of the SSPCON2 register allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence. 15.3.4.
PIC18F/LF1XK50 15.3.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCL output is forced to ‘0’. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL.
DS41350E-page 162 Preliminary CKP SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 2 A6 3 4 A4 5 A3 6 A2 Receiving Address A5 7 A1 8 9 ACK R/W = 0 3 4 D4 5 D3 Receiving Data D5 Cleared by software 2 D6 If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to ‘0’ and no clock stretching will occur SSPBUF is read 1 D7 6 D2 7 D1 9 ACK 1 D7 BF is set after falling edge of the 9th clock, CKP is reset to ‘0’ and clock stretc
2010 Microchip Technology Inc.
PIC18F/LF1XK50 15.3.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices.
PIC18F/LF1XK50 MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled.
PIC18F/LF1XK50 15.3.6.1 I2C Master Mode Operation A typical transmit sequence would go as follows: The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock.
PIC18F/LF1XK50 15.3.7 BAUD RATE 2 In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the SSPADD register (Figure 15-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting. Table 15-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPADD. EQUATION 15-1: Once the given operation is complete (i.e.
PIC18F/LF1XK50 15.3.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting.
PIC18F/LF1XK50 I2C MASTER MODE START CONDITION TIMING Note: To initiate a Start condition, the user sets the Start Enable bit, SEN bit of the SSPCON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low.
PIC18F/LF1XK50 15.3.9 I2C MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit of the SSPCON2 register is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting.
PIC18F/LF1XK50 15.3.10 I2C MASTER MODE TRANSMISSION 15.3.10.3 Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full flag bit, BF and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter SP106).
DS41350E-page 172 S Preliminary R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared by software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPBUF written 1 D7 1 SCL held low while CPU responds to SSPIF ACK = 0 R/W = 0 SSPBUF written with 7-bit address and R/W start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPBUF is written by software Cleared by software service routine from SSP interrupt 2 D6 Tran
2010 Microchip Technology Inc.
PIC18F/LF1XK50 15.3.12 ACKNOWLEDGE SEQUENCE TIMING 15.3.13 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPCON2 register. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’.
PIC18F/LF1XK50 15.3.14 SLEEP OPERATION 15.3.17 2 While in Sleep mode, the I C Slave module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 15.3.15 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 15.3.
PIC18F/LF1XK50 15.3.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 15-26). SCL is sampled low before SDA is asserted low (Figure 15-27). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 15-28).
PIC18F/LF1XK50 FIGURE 15-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
PIC18F/LF1XK50 15.3.17.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 15-29). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time.
PIC18F/LF1XK50 15.3.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 15-31).
PIC18F/LF1XK50 TABLE 15-4: SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288 288 Name IPR2 OSCFIP C1IP C2IP EEIP BCLIP USBIP TMR3IP — PIR2 OSCFIF C1IF C2IF EEIF BCLIF USBIF TMR3IF — 288 PIE2 OSCFIE C1IE C2IE EEIE BCLIE USBIE
PIC18F/LF1XK50 16.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The EUSART module includes the following capabilities: • • • • • • • • • • The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution.
PIC18F/LF1XK50 FIGURE 16-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN RX/DT pin Baud Rate Generator Data Recovery FOSC SPBRGH SPBRG x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 (8) ••• 7 1 LSb 0 START RX9 ÷n BRG16 Multiplier Stop RCIDL RSR Register MSb Pin Buffer and Control +1 OERR n FERR RX9D RCREG Register FIFO 8 Data Bus RCIF RCIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Re
PIC18F/LF1XK50 16.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission.
PIC18F/LF1XK50 16.1.1.4 Transmit Interrupt Flag 16.1.1.6 The TXIF interrupt flag bit of the PIR1 register is set whenever the EUSART transmitter is enabled and no character is being held for transmission in the TXREG. In other words, the TXIF bit is only clear when the TSR is busy with a character and a new character has been queued for transmission in the TXREG. The TXIF flag bit is not cleared immediately upon writing TXREG.
PIC18F/LF1XK50 FIGURE 16-3: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (Shift Clock) RB7/TX/CK pin Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer Reg. Empty Flag) 1 TCY Word 1 Transmit Shift Reg TRMT bit (Transmit Shift Reg. Empty Flag) FIGURE 16-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG Word 1 BRG Output (Shift Clock) RB7/TX/CK pin Word 2 Start bit bit 0 bit 1 Word 1 1 TCY TXIF bit (Interrupt Reg.
PIC18F/LF1XK50 16.1.2 EUSART ASYNCHRONOUS RECEIVER 16.1.2.2 The Asynchronous mode would typically be used in RS-232 systems. The receiver block diagram is shown in Figure 16-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate.
PIC18F/LF1XK50 16.1.2.4 Receive Interrupts 16.1.2.7 The RCIF interrupt flag bit of the PIR1 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software.
PIC18F/LF1XK50 16.1.2.9 Asynchronous Reception Set-up: 16.1.2.10 1. Initialize the SPBRGH:SPBRG register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 16.3 “EUSART Baud Rate Generator (BRG)”). 2. Enable the serial port by setting the SPEN bit and the RX/DT pin TRIS bit. The SYNC bit must be clear for asynchronous operation. 3. If interrupts are desired, set the RCIE interrupt enable bit and set the GIE and PEIE bits of the INTCON register. 4.
PIC18F/LF1XK50 TABLE 16-2: Name INTCON REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285 Bit 6 GIE/GIEH PEIE/GIEL PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 287 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
PIC18F/LF1XK50 16.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (HFINTOSC). However, the HFINTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. REGISTER 16-1: The first (preferred) method uses the OSCTUNE register to adjust the HFINTOSC output.
PIC18F/LF1XK50 REGISTER 16-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6
PIC18F/LF1XK50 REGISTER 16-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bit 6 R
PIC18F/LF1XK50 16.3 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCON register selects 16-bit mode. If the system clock is changed during an active receive operation, a receive error or data loss may result.
PIC18F/LF1XK50 TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 48.000 MHz FOSC = 18.432 MHz FOSC = 12.000 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 — — — 1200 0.00 239 1202 0.16 155 1200 0.00 143 Actual Rate % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 2400 — — — 2400 0.00 119 2404 0.
PIC18F/LF1XK50 TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 — — — — — — — 1202 — 0.16 — 207 — 1200 — 0.00 — 191 300 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.
PIC18F/LF1XK50 TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 48.000 MHz FOSC = 18.432 MHz FOSC = 12.000 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRGH :SPBRG (decimal) 300 1200 300 1200 0.00 0.00 39999 9999 300.0 1200 0.00 0.00 15359 3839 300 1200 0.00 0.00 9999 2499 300.0 1200 0.00 0.00 9215 2303 2400 2400 0.00 4999 2400 0.00 1919 2400 0.00 1249 2400 0.
PIC18F/LF1XK50 16.3.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. and SPBRG registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. Note 1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see Section 16.3.3 “Auto-Wake-up on Break”). In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed.
PIC18F/LF1XK50 16.3.2 AUTO-BAUD OVERFLOW 16.3.3.1 During the course of automatic baud detection, the ABDOVF bit of the BAUDCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRG register pair. After the ABDOVF has been set, the counter continues to count until the fifth rising edge is detected on the RX pin.
PIC18F/LF1XK50 FIGURE 16-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RX/DT Line RCIF Note 1: Cleared due to User Read of RCREG The EUSART remains in Idle while the WUE bit is set.
PIC18F/LF1XK50 16.3.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXSTA register. The Break character transmission is then initiated by a write to the TXREG. The value of data written to TXREG will be ignored and all ‘0’s will be transmitted.
PIC18F/LF1XK50 16.4 16.4.1.2 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line.
PIC18F/LF1XK50 16.4.1.5 1. 2. Synchronous Master Transmission Set-up: 3. Initialize the SPBRGH, SPBRG register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 16.3 “EUSART Baud Rate Generator (BRG)”). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Set the TRIS bits corresponding to the RX/DT and TX/CK I/O pins. 4. 5. 6. FIGURE 16-10: 7. 8. Disable Receive mode by clearing bits SREN and CREN. Enable Transmit mode by setting the TXEN bit.
PIC18F/LF1XK50 TABLE 16-7: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INT0IE RABIE TMR0IF INT0IF RABIF 285 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288 IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288 INTCON GIE/GIEH PEIE/GIEL TMR0IE Bit 4 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 287 TRISC TRISC7 T
PIC18F/LF1XK50 16.4.1.9 Receiving 9-bit Characters 16.4.1.10 The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the EUSART will shift 9-bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the 8 Least Significant bits from the RCREG.
PIC18F/LF1XK50 TABLE 16-8: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288 IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D INTCON RCSTA RCREG TXSTA GIE/GIEH PEIE/GIEL EUSART Rece
PIC18F/LF1XK50 TABLE 16-9: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INT0IE RABIE TMR0IF INT0IF RABIF 285 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288 IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288 INTCON GIE/GIEH PEIE/GIEL TMR0IE Bit 4 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 287 TRISC TRISC7 TR
PIC18F/LF1XK50 TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name INTCON Bit 7 Bit 6 Bit 5 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INT0IE RABIE TMR0IF INT0IF RABIF 285 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288 IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 287 RCSTA RCREG GIE/GIEH PEIE/GIEL TMR0IE Bit 4 EUSART Receive
PIC18F/LF1XK50 NOTES: DS41350E-page 208 Preliminary 2010 Microchip Technology Inc.
PIC18F/LF1XK50 17.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
PIC18F/LF1XK50 17.1 17.1.4 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Results formatting 17.1.1 PORT CONFIGURATION The ANSEL, ANSELH, TRISA, TRISB and TRISE registers all configure the A/D port pins.
PIC18F/LF1XK50 17.1.6 INTERRUPTS This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the global interrupt must be disabled. If the global interrupt is enabled, execution will switch to the Interrupt Service Routine.
PIC18F/LF1XK50 17.2 ADC Operation 17.2.1 Figure 17-3 shows the operation of the A/D converter after the GO bit has been set and the ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into SLEEP mode before the conversion begins. STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’.
PIC18F/LF1XK50 17.2.2 COMPLETION OF A CONVERSION When the conversion is complete, the ADC module will: • Clear the GO/DONE bit • Set the ADIF flag bit • Update the ADRESH:ADRESL registers with new conversion result 17.2.3 DISCHARGE The discharge phase is used to initialize the value of the capacitor array. The array is discharged after every sample.
PIC18F/LF1XK50 17.2.9 A/D CONVERSION PROCEDURE EXAMPLE 17-1: This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8.
PIC18F/LF1XK50 17.2.10 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC. Note: Analog pin control is performed by the ANSEL and ANSELH registers. For ANSEL and ANSELH registers, see Register 9-15 and Register 9-16, respectively.
PIC18F/LF1XK50 REGISTER 17-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — PVCFG1 PVCFG0 NVCFG1 NVCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 PVCFG<1:0>: Positive Voltage Reference select bit 00 = Positive voltage reference supplied internally by VDD.
PIC18F/LF1XK50 REGISTER 17-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 x = Bit is unknown ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition time se
PIC18F/LF1XK50 REGISTER 17-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 17-5: ADRESL: ADC RESULT REGISTER LOW
PIC18F/LF1XK50 17.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 17-5. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 17-5.
PIC18F/LF1XK50 FIGURE 17-5: ANALOG INPUT MODEL VDD ANx Rs CPIN 5 pF VA VT = 0.6V VT = 0.6V RIC 1k Sampling Switch SS Rss CHOLD = 13.5 pF I LEAKAGE(1) Discharge Switch Note 1: VDD Legend: CPIN = Input Capacitance = Threshold Voltage VT I LEAKAGE = Leakage current at the pin due to various junctions RIC = Interconnect Resistance SS = Sampling Switch CHOLD = Sample/Hold Capacitance VSS/VREF- 3.5V 3.0V 2.5V 2.0V 1.5V .1 1 10 Rss (k) 100 See Section 27.0 “Electrical Specifications”.
PIC18F/LF1XK50 TABLE 17-2: Name INTCON REGISTERS ASSOCIATED WITH A/D OPERATION Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 285 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 288 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 288 IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 288 ADRESH A/D Result Register, High Byte 287 ADRESL A/D Result Register, Low Byte 287 ADCON
PIC18F/LF1XK50 NOTES: DS41350E-page 222 Preliminary 2010 Microchip Technology Inc.
PIC18F/LF1XK50 18.0 COMPARATOR MODULE FIGURE 18-1: Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. The comparators are very useful mixed signal building blocks because they provide analog functionality independent of the program execution.
PIC18F/LF1XK50 FIGURE 18-2: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM C1CH<1:0> 2 D AGND Q1 0 To Data Bus Q EN RD_CM1CON0 C12IN1C12IN2- 1 MUX 2 C12IN3- 3 Set C1IF D Q3*RD_CM1CON0 Q EN CL NReset C1ON(1) C1R C1VINC1IN+ VREF FVR 0 MUX 1 C1VIN+ 0 MUX C1VREF 1 - C1SP To PWM Logic C1OUT C1 + C1POL C1SYNC C2OE C1OE 0 C1RSEL D From TMR1L[0] Q 1 C12OUT (4) SYNCC1OUT Note 1: 2: 3: 4: DS41350E-page 224 When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.
PIC18F/LF1XK50 FIGURE 18-3: COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM D Q1 To Data Bus Q EN RD_CM2CON0 C2CH<1:0> Set C2IF 2 D Q Q3*RD_CM2CON0 AGND C12IN1C12IN2- 1 MUX 2 C12IN3- 3 EN CL NRESET C2ON(1) 0 C2VINC2VIN+ To PWM Logic C2OUT C2 C2SP C2SYNC C2R C2POL 0 C2IN+ VREF FVR 0 MUX 1 0 MUX C2VREF 1 D From TMR1L[0] Q C20E C12OUT pin 1 (4) SYNCC2OUT C2RSEL Note 1: 2: 3: 4: 2010 Microchip Technology Inc.
PIC18F/LF1XK50 18.2 TABLE 18-1: Comparator Control Each comparator has a separate control and Configuration register: CM1CON0 for Comparator C1 and CM2CON0 for Comparator C2. In addition, Comparator C2 has a second control register, CM2CON1, for controlling the interaction with Timer1 and simultaneous reading of both comparator outputs.
PIC18F/LF1XK50 18.4 18.4.1 Comparator Interrupt Operation The comparator interrupt flag can be set whenever there is a change in the output value of the comparator. Changes are recognized by means of a mismatch circuit which consists of two latches and an exclusiveor gate (see Figure 18-2 and Figure 18-3). One latch is updated with the comparator output level when the CMxCON0 register is read. This latch retains the value until the next read of the CMxCON0 register or the occurrence of a Reset.
PIC18F/LF1XK50 18.5 Operation During Sleep The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in the Section 27.0 “Electrical Specifications”. If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator. Each comparator is turned off by clearing the CxON bit of the CMxCON0 register.
PIC18F/LF1XK50 REGISTER 18-1: CM1CON0: COMPARATOR 1 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C1ON: Comparator C1 Enable bit 1 = Comparator C1 is enabled 0 = Comparator C1 is disabled bit 6 C1OUT: Comparator C1 Output bit If C1POL = 1 (inverted polarity): C1OUT = 0
PIC18F/LF1XK50 REGISTER 18-2: CM2CON0: COMPARATOR 2 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C2ON: Comparator C2 Enable bit 1 = Comparator C2 is enabled 0 = Comparator C2 is disabled bit 6 C2OUT: Comparator C2 Output bit If C2POL = 1 (inverted polarity): C2OUT = 0
PIC18F/LF1XK50 18.7 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 18-6. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur.
PIC18F/LF1XK50 18.8 Additional Comparator Features There are four additional comparator features: • • • • Simultaneous read of comparator outputs Internal reference selection Hysteresis selection Output Synchronization 18.8.1 SIMULTANEOUS COMPARATOR OUTPUT READ The MC1OUT and MC2OUT bits of the CM2CON1 register are mirror copies of both comparator outputs. The ability to read both outputs simultaneously from a single register eliminates the timing skew of reading separate registers.
PIC18F/LF1XK50 REGISTER 18-3: CM2CON1: COMPARATOR 2 CONTROL REGISTER 1 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MC1OUT: Mirror Copy of C1OUT bit bit 6 MC2OUT: Mirror Copy of C2OUT bit bit 5 C1RSEL: Comparator C1 Reference Select bit 1 = FVR routed to C1VREF input 0 = CVREF
PIC18F/LF1XK50 TABLE 18-3: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 288 CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 288 CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC 288 REFCON0 FVR1EN FVR1ST FVR1S1 FVR1S0 — — — — 287 REFCON1 D1EN D1LPS DAC1OE --- D1PSS1 D1PSS0 — D1NSS 287 TMR0IE INT0IE RABIE TM
PIC18F/LF1XK50 19.0 POWER-MANAGED MODES 19.1.1 The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are: PIC18F/LF1XK50 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices).
PIC18F/LF1XK50 19.1.3 MULTIPLE FUNCTIONS OF THE SLEEP COMMAND 19.2.3 The power-managed mode that is invoked with the SLEEP instruction is determined by the setting of the IDLEN bit of the OSCCON register at the time the instruction is executed. All clocks stop and minimum power is consumed when SLEEP is executed with the IDLEN bit cleared. The system clock continues to supply a clock to the peripherals but is disconnected from the CPU when SLEEP is executed with the IDLEN bit set. 19.
PIC18F/LF1XK50 19.3 Sleep Mode 19.4 The Power-Managed Sleep mode in the PIC18F/ LF1XK50 devices is identical to the legacy Sleep mode offered in all other PIC® microcontroller devices. It is entered by clearing the IDLEN bit of the OSCCON register and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 19-1) and all clock source status bits are cleared.
PIC18F/LF1XK50 19.4.1 PRI_IDLE MODE 19.4.2 This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “warm-up” or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction.
PIC18F/LF1XK50 19.4.3 RC_IDLE MODE 19.5.1 In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block from the HFINTOSC multiplexer output. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then set the SCS1 bit and execute SLEEP.
PIC18F/LF1XK50 19.5.3 EXIT BY RESET 19.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Exiting Sleep and Idle modes by Reset causes code execution to restart at address 0. See Section 23.0 “Reset” for more details. Certain exits from power-managed modes do not invoke the OST at all. There are two cases: The exit delay time from Reset to the start of code execution depends on both the clock sources before and after the wake-up and the type of oscillator. Exit delays are summarized in Table 19-2.
PIC18F/LF1XK50 20.0 SR LATCH 20.2 The SRQEN and SRNQEN bits of the SRCON0 register control the latch output selection. Only one of the SR latch’s outputs may be directly output to an I/O pin at a time. Priority is determined by the state of bits SRQEN and SRNQEN in registers SRCON0. The module consists of a single SR Latch with multiple Set and Reset inputs as well as selectable latch output.
PIC18F/LF1XK50 TABLE 20-2: SRCLK FREQUENCY TABLE SRCLK Divider FOSC = 20 MHz FOSC = 16 MHz 111 512 25.6 s 32 s 110 256 12.8 s 16 s 32 s 64 s 256 s 101 128 6.4 s 8 s 16 s 32 s 128 s FOSC = 8 MHz FOSC = 4 MHz 64 s 128 s FOSC = 1 MHz 512 s 100 64 3.2 s 4 s 8 s 16 s 64 s 011 32 1.6 s 2 s 4 s 8 s 32 s 010 16 0.8 s 1 s 2 s 4 s 16 s 001 8 0.4 s 0.5 s 1 s 2 s 8 s 000 4 0.2 s 0.25 s 0.
PIC18F/LF1XK50 REGISTER 20-2: SRCON1: SR LATCH CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SRSPE: SR Latch Peripheral Set Enable bit 1 = INT1 pin status sets SR Latch 0 = INT1pin status has no effect on SR Latch bit 6 SRSCKE: SR
PIC18F/LF1XK50 NOTES: DS41350E-page 244 Preliminary 2010 Microchip Technology Inc.
PIC18F/LF1XK50 21.0 VOLTAGE REFERENCES 21.1.1 There are two independent voltage references available: • Programmable Voltage Reference • 1.024V Fixed Voltage Reference 21.1 Voltage Reference The Voltage Reference module provides an internally generated voltage reference for the comparators and the DAC module. The following features are available: • • • • • Independent from Comparator operation Single 32-level voltage ranges Output clamped to VSS Ratiometric with VDD 1.
PIC18F/LF1XK50 21.2 21.2.1 FVR Reference Module The FVR reference is a stable fixed voltage reference, independent of VDD, with a nominal output voltage of 1.024V. This reference can be enabled by setting the FVR1EN bit of the REFCON0 register to ‘1’. The FVR voltage reference can be routed to the comparators or an ADC input channel.
PIC18F/LF1XK50 FIGURE 21-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC18F1XK50/ PIC18LF1XK50 CVREF Module R(1) Voltage Reference Output Impedance Note 1: + – CVREF Buffered CVREF Output R is dependent upon the voltage reference Configuration bits, CVR<3:0> and CVRR.
PIC18F/LF1XK50 REGISTER 21-2: REFCON1: REFERENCE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 D1EN D1LPS DAC1OE --- D1PSS1 D1PSS0 --- D1NSS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 D1EN: DAC 1 Enable bit 0 = DAC 1 is disabled 1 = DAC 1 is enabled bit 6 D1LPS: DAC 1 Low-Power Voltage State Select bit 0 = VDAC = DAC1 Negative reference
PIC18F/LF1XK50 TABLE 21-1: Name REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page REFCON0 FVR1EN FVR1ST FVR1S1 FVR1S0 — — — — 287 REFCON1 D1EN D1LPS DAC1OE --- D1PSS1 D1PSS0 — D1NSS 287 REFCON2 — — — DAC1R4 DAC1R3 DAC1R2 DAC1R1 DAC1R0 287 TRISC0 288 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 Legend: Shaded cells are not used with the comparator voltage reference.
PIC18F/LF1XK50 NOTES: DS41350E-page 250 Preliminary 2010 Microchip Technology Inc.
PIC18F/LF1XK50 22.0 UNIVERSAL SERIAL BUS (USB) 22.1 PIC18F1XK50/PIC18LF1XK50 devices contain a full-speed and low-speed, compatible USB Serial Interface Engine (SIE) that allows fast communication between any USB host and the PIC® microcontroller. The SIE can be interfaced directly to the USB by utilizing the internal transceiver. This section describes the details of the USB peripheral. Because of the very specific nature of the module, knowledge of USB is expected.
PIC18F/LF1XK50 22.2 USB Status and Control In addition, the USB Control register contains a status bit, SE0 (UCON<5>), which is used to indicate the occurrence of a single-ended zero on the bus. When the USB module is enabled, this bit should be monitored to determine whether the differential data lines have come out of a single-ended zero condition. This helps to differentiate the initial power-up state from the USB Reset signal.
PIC18F/LF1XK50 The PPBRST bit (UCON<6>) controls the Reset status when Double-Buffering mode (ping-pong buffering) is used. When the PPBRST bit is set, all Ping-Pong Buffer Pointers are set to the Even buffers. PPBRST has to be cleared by firmware. This bit is ignored in buffering modes not using ping-pong buffering. The PKTDIS bit (UCON<4>) is a flag indicating that the SIE has disabled packet transmission and reception. This bit is set by the SIE when a SETUP token is received to allow setup processing.
PIC18F/LF1XK50 REGISTER 22-2: R/W-0 UCFG: USB CONFIGURATION REGISTER U-0 UTEYE — U-0 — R/W-0 UPUEN (1) U-0 — R/W-0 (1) FSEN R/W-0 R/W-0 PPB1 PPB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UTEYE: USB Eye Pattern Test Enable bit 1 = Eye pattern test enabled 0 = Eye pattern test disabled bit 6-5 Unimplemented: Read as ‘0’ bit 4 UPUEN: USB On-Chip Pull-up En
PIC18F/LF1XK50 22.2.2.2 Internal Pull-up Resistors 22.2.2.4 The PIC18F1XK50/PIC18LF1XK50 devices have built-in pull-up resistors designed to meet the requirements for low-speed and full-speed USB. The UPUEN bit (UCFG<4>) enables the internal pull-ups. Figure 22-1 shows the pull-ups and their control. Note: 22.2.2.3 The official USB specifications require that USB devices must never source any current onto the +5V VBUS line of the USB cable.
PIC18F/LF1XK50 22.2.3 USB STATUS REGISTER (USTAT) Clearing the transfer complete flag bit, TRNIF, causes the SIE to advance the FIFO. If the next data in the FIFO holding register is valid, the SIE will reassert the interrupt within 6 TCY of clearing TRNIF. If no additional data is present, TRNIF will remain clear; USTAT data will no longer be reliable. The USB Status register reports the transaction status within the SIE.
PIC18F/LF1XK50 22.2.4 USB ENDPOINT CONTROL Each of the 8 possible bidirectional endpoints has its own independent control register, UEPn (where ‘n’ represents the endpoint number). Each register has an identical complement of control bits. The prototype is shown in Register 22-4. The EPHSHK bit (UEPn<4>) controls handshaking for the endpoint; setting this bit enables USB handshaking. Typically, this bit is always set except when using isochronous endpoints.
PIC18F/LF1XK50 22.2.5 USB ADDRESS REGISTER (UADDR) FIGURE 22-4: The USB Address register contains the unique USB address that the peripheral will decode when active. UADDR is reset to 00h when a USB Reset is received, indicated by URSTIF, or when a Reset is received from the microcontroller. The USB address must be written by the microcontroller during the USB setup phase (enumeration) as part of the Microchip USB firmware support. 22.2.
PIC18F/LF1XK50 22.4 Buffer Descriptors and the Buffer Descriptor Table The registers in Bank 2 are used specifically for endpoint buffer control in a structure known as the Buffer Descriptor Table (BDT). This provides a flexible method for users to construct and control endpoint buffers of various lengths and configuration. FIGURE 22-5: Address The BDT is composed of Buffer Descriptors (BD) which are used to define and control the actual buffers in the USB RAM space.
PIC18F/LF1XK50 The BDnSTAT byte of the BDT should always be the last byte updated when preparing to arm an endpoint. The SIE will clear the UOWN bit when a transaction has completed. No hardware mechanism exists to block access when the UOWN bit is set. Thus, unexpected behavior can occur if the microcontroller attempts to modify memory when the SIE owns it. Similarly, reading such memory may produce inaccurate data until the USB peripheral returns ownership to the microcontroller. 22.4.1.
PIC18F/LF1XK50 REGISTER 22-5: R/W-x UOWN(1) BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH BD31STAT), CPU MODE (DATA IS WRITTEN TO THE SIDE) R/W-x U-0 U-0 (2) (3) (3) DTS — — R/W-x R/W-x R/W-x R/W-x DTSEN BSTALL BC9 BC8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 UOWN: USB Own bit(1) 0 = The microcontroller core owns the BD and its correspon
PIC18F/LF1XK50 22.4.1.3 BDnSTAT Register (SIE Mode) When the BD and its buffer are owned by the SIE, most of the bits in BDnSTAT take on a different meaning. The configuration is shown in Register 22-6. Once the UOWN bit is set, any data or control settings previously written there by the user will be overwritten with data from the SIE. The BDnSTAT register is updated by the SIE with the token Packet Identifier (PID) which is stored in BDnSTAT<5:3>.
PIC18F/LF1XK50 22.4.4 PING-PONG BUFFERING the completion of a transaction (UOWN cleared by the SIE), the pointer is toggled to the Odd BD. After the completion of the next transaction, the pointer is toggled back to the Even BD and so on. An endpoint is defined to have a ping-pong buffer when it has two sets of BD entries: one set for an Even transfer and one set for an Odd transfer. This allows the CPU to process one BD while the SIE is processing the other BD.
PIC18F/LF1XK50 TABLE 22-2: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT BUFFERING MODES BDs Assigned to Endpoint Mode 0 (No Ping-Pong) Endpoint Mode 1 (Ping-Pong on EP0 OUT) Mode 3 (Ping-Pong on all other EPs, except EP0) Mode 2 (Ping-Pong on all EPs) Out In Out In Out In Out 0 0 1 0 (E), 1 (O) 1 2 3 3 2 4 5 5 6 8 (E), 9 (O) 10 (E), 11 (O) 3 6 7 7 8 12 (E), 13 (O) 14 (E), 15 (O) In 2 0 (E), 1 (O) 2 (E), 3 (O) 0 1 4 4 (E), 5 (O) 6 (E), 7 (O) 2 (E), 3 (O) 4
PIC18F/LF1XK50 22.5 USB Interrupts Figure 22-7 shows the interrupt logic for the USB module. There are two layers of interrupt registers in the USB module. The top level consists of overall USB Status interrupts; these are enabled and flagged in the UIE and UIR registers, respectively. The second level consists of USB error conditions, which are enabled and flagged in the UEIR and UEIE registers. An interrupt condition in any of these triggers a USB Error Interrupt Flag (UERRIF) in the top level.
PIC18F/LF1XK50 22.5.1 USB INTERRUPT STATUS REGISTER (UIR) Once an interrupt bit has been set by the SIE, it must be cleared by software by writing a ‘0’. The flag bits can also be set in software which can aid in firmware debugging. The USB Interrupt Status register (Register 22-7) contains the flag bits for each of the USB Status interrupt sources. Each of these sources has a corresponding interrupt enable bit in the UIE register.
PIC18F/LF1XK50 22.5.1.1 Bus Activity Detect Interrupt Bit (ACTVIF) The ACTVIF bit cannot be cleared immediately after the USB module wakes up from Suspend or while the USB module is suspended. A few clock cycles are required to synchronize the internal hardware state machine before the ACTVIF bit can be cleared by firmware. Clearing the ACTVIF bit before the internal hardware is synchronized may not have an effect on the value of ACTVIF.
PIC18F/LF1XK50 22.5.2 USB INTERRUPT ENABLE REGISTER (UIE) The USB Interrupt Enable register (Register 22-8) contains the enable bits for the USB Status interrupt sources. Setting any of these bits will enable the respective interrupt source in the UIR register. REGISTER 22-8: The values in this register only affect the propagation of an interrupt condition to the microcontroller’s interrupt logic.
PIC18F/LF1XK50 22.5.3 USB ERROR INTERRUPT STATUS REGISTER (UEIR) The USB Error Interrupt Status register (Register 22-9) contains the flag bits for each of the error sources within the USB peripheral. Each of these sources is controlled by a corresponding interrupt enable bit in the UEIE register. All of the USB error flags are ORed together to generate the USB Error Interrupt Flag (UERRIF) at the top level of the interrupt logic.
PIC18F/LF1XK50 22.5.4 USB ERROR INTERRUPT ENABLE REGISTER (UEIE) As with the UIE register, the enable bits only affect the propagation of an interrupt condition to the microcontroller’s interrupt logic. The flag bits are still set by their interrupt conditions, allowing them to be polled and serviced without actually generating an interrupt. The USB Error Interrupt Enable register (Register 22-10) contains the enable bits for each of the USB error interrupt sources.
PIC18F/LF1XK50 22.6 22.6.2 USB Power Modes Many USB applications will likely have several different sets of power requirements and configuration. The most common power modes encountered are Bus Power Only, Self-Power Only and Dual Power with Self-Power Dominance. The most common cases are presented here. Also provided is a means of estimating the current consumption of the USB transceiver. 22.6.1 BUS POWER ONLY In Bus Power Only mode, all power for the application is drawn from the USB (Figure 22-9).
PIC18F/LF1XK50 22.6.3 DUAL POWER WITH SELF-POWER DOMINANCE 22.6.4 USB TRANSCEIVER CURRENT CONSUMPTION Some applications may require a dual power option. This allows the application to use internal power primarily, but switch to power from the USB when no internal power is available. Figure 22-11 shows a simple Dual Power with Self-Power Dominance mode example, which automatically switches between Self-Power Only and USB Bus Power Only modes.
PIC18F/LF1XK50 EQUATION 22-1: ESTIMATING USB TRANSCEIVER CURRENT CONSUMPTION IXCVR = Legend: (60 mA • VUSB • PZERO • PIN • LCABLE) + IPULLUP (3.3V • 5m) VUSB: Voltage applied to the VUSB pin in volts. (Should be 3.0V to 3.6V.) PZERO: Percentage (in decimal) of the IN traffic bits sent by the PIC® device that are a value of ‘0’. PIN: Percentage (in decimal) of total bus bandwidth that is used for IN traffic. LCABLE: Length (in meters) of the USB cable. The USB 2.
PIC18F/LF1XK50 22.7 Oscillator The USB module has specific clock requirements. For full-speed operation, the clock source must be 48 MHz. Even so, the microcontroller core and other peripherals are not required to run at that clock speed. Available clocking options are described in detail in Section 2.11 “USB Operation”. 22.8 Interrupt-On-Change for D+/Dpins The PIC18F/LF1XK50 has interrupt-on-change functionality on both D+ and D- data pins.
PIC18F/LF1XK50 22.10 Overview of USB 22.10.3 This section presents some of the basic USB concepts and useful information necessary to design a USB device. Although much information is provided in this section, there is a plethora of information provided within the USB specifications and class specifications. Thus, the reader is encouraged to refer to the USB specifications for more information (www.usb.org).
PIC18F/LF1XK50 The USB specification limits the power taken from the bus. Each device is ensured 100 mA at approximately 5V (one unit load). Additional power may be requested, up to a maximum of 500 mA. Note that power above one unit load is a request and the host or hub is not obligated to provide the extra current. Thus, a device capable of consuming more than one unit load must be able to maintain a low-power configuration of a one unit load or less, if necessary.
PIC18F/LF1XK50 23.0 RESET A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 23-1.
PIC18F/LF1XK50 REGISTER 23-1: R/W-0 IPEN RCON: RESET CONTROL REGISTER R/W-1 SBOREN U-0 (1) — R/W-1 RI R-1 TO R-1 R/W-0 PD (2) R/W-0 POR bit 7 BOR bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts bit 6 SBOREN: BOR Software Enable bit(1) If BOREN<1:0> = 0
PIC18F/LF1XK50 23.2 FIGURE 23-2: Master Clear (MCLR) The MCLR pin provides a method for triggering an external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. 23.3 VDD VDD PIC® MCU The MCLR pin is not driven low by any internal Resets, including the WDT. In PIC18F/LF1XK50 devices, the MCLR input can be disabled with the MCLRE Configuration bit.
PIC18F/LF1XK50 23.4 23.4.1 Brown-out Reset (BOR) PIC18F/LF1XK50 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV<1:0> and BOREN<1:0> bits of the CONFIG2L Configuration register. There are a total of four BOR configurations which are summarized in Table 23-1. The BOR threshold is set by the BORV<1:0> bits.
PIC18F/LF1XK50 23.5 23.5.2 Device Reset Timers OSCILLATOR START-UP TIMER (OST) PIC18F/LF1XK50 devices incorporate three separate on-chip timers that help regulate the Power-on Reset process. Their main function is to ensure that the device clock is stable before code is executed. These timers are: The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized.
PIC18F/LF1XK50 FIGURE 23-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 23-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 23-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS41350E-page 282 Prelim
PIC18F/LF1XK50 FIGURE 23-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) FIGURE 23-7: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL 2 ms max. First three stages of the PWRT timer. 2010 Microchip Technology Inc.
PIC18F/LF1XK50 23.6 Reset State of Registers Some registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. All other registers are forced to a “Reset state” depending on the type of Reset that occurred. Table 23-4 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups.
PIC18F/LF1XK50 TABLE 23-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS Address Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets TOSU FFFh ---0 0000 ---0 0000 ---0 uuuu(3) TOSH FFEh 0000 0000 0000 0000 uuuu uuuu(3) TOSL FFDh 0000 0000 0000 0000 uuuu uuuu(3) STKPTR FFCh 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU FFBh ---0 0000 ---0 0000 ---u uuuu PCLATH FFAh 0000 0000 0000 0000 uuuu uuuu PCL FF9h 0000 0000 0000 0000 TBLPTRU FF8h ---0
PIC18F/LF1XK50 TABLE 23-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Address Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt FSR1H FE2h ---- 0000 ---- 0000 ---- uuuu FSR1L FE1h xxxx xxxx uuuu uuuu uuuu uuuu BSR FE0h ---- 0000 ---- 0000 ---- uuuu INDF2 FDFh N/A N/A N/A POSTINC2 FDEh N/A N/A N/A POSTDEC2 FDDh N/A N/A N/A PREINC2 FDCh N/A N/A N/A PLUSW2 Register FDBh N/A N/A N/A FSR2
PIC18F/LF1XK50 TABLE 23-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Address Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt ADRESH FC4h xxxx xxxx uuuu uuuu uuuu uuuu ADRESL FC3h xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 FC2h --00 0000 --00 0000 --uu uuuu ADCON1 FC1h ---- 0000 ---- 0000 ---- uuuu ADCON2 FC0h 0-00 0000 0-00 0000 u-uu uuuu CCPR1H FBFh xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L FBEh xxx
PIC18F/LF1XK50 TABLE 23-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Address Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt IPR2 FA2h 1111 111- 1111 111- uuuu uuu- PIR2 FA1h 0000 000- 0000 000- uuuu uuu-(1) PIE2 FA0h 0000 000- 0000 000- uuuu uuu- IPR1 F9Fh -111 1111 -111 1111 -uuu uuuu PIR1 F9Eh -000 0000 -000 0000 -uuu uuuu(1) PIE1 F9Dh -000 0000 -000 0000 -uuu uuuu OSCTUNE F9Bh 0000 000
PIC18F/LF1XK50 TABLE 23-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Address Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt USTAT F63h -xxx xxx- -xxx xxx- -uuu uuu- UIR F62h -000 0000 -000 0000 -uuu uuuu UCFG F61h 0--0 -000 0--0 -000 u--u -uuu UIE F60h -000 0000 -000 0000 -uuu uuuu UEIR F5Fh 0--0 0000 0--0 0000 u--u uuuu UFRMH F5Eh ---- -xxx ---- -xxx ---- -uuu UFRML F5Dh xxxx xxxx xxxx
PIC18F/LF1XK50 NOTES: DS41350E-page 290 Preliminary 2010 Microchip Technology Inc.
PIC18F/LF1XK50 24.0 SPECIAL FEATURES OF THE CPU PIC18F/LF1XK50 devices include several features intended to maximize reliability and minimize cost through elimination of external components.
PIC18F/LF1XK50 24.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’) or left unprogrammed (read as ‘1’) to select various device configurations. These bits are mapped starting at program memory location 300000h. The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (300000h-3FFFFFh), which can only be accessed using table reads and table writes.
PIC18F/LF1XK50 REGISTER 24-1: CONFIG1L: CONFIGURATION REGISTER 1 LOW U-0 U-0 R/P-0 R/P-0 R/P-0 U-0 U-0 U-0 — — USBDIV CPUDIV1 CPUDIV0 — — — bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 USBDIV: USB Clock Selection bit Selects the clock source for Low-speed USB operation 1 = USB clock comes from the OSC1/OSC2 divided by 2 0 = USB clock co
PIC18F/LF1XK50 REGISTER 24-2: CONFIG1H: CONFIGURATION REGISTER 1 HIGH R/P-0 R/P-0 R/P-1 R/P-0 R/P-0 R/P-1 R/P-1 R/P-1 IESO FCMEN PCLKEN PLLEN FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ x = Bit is unknown bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode enabled 0 = Oscillator Switchover mode disabled bit 6 FCMEN: Fail-Safe Clock Moni
PIC18F/LF1XK50 REGISTER 24-3: U-0 CONFIG2L: CONFIGURATION REGISTER 2 LOW U-0 — — U-0 — R/P-1 BORV1 R/P-1 (1) BORV0 (1) R/P-1 BOREN1 R/P-1 (2) R/P-1 BOREN0 bit 7 (2) PWRTEN(2) bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-3 BORV<1:0>: Brown-out Reset Voltage bits(1) 11 = VBOR set to 1.9V nominal 10 = VBOR set to 2.2V nominal 01 = VBOR set to 2.
PIC18F/LF1XK50 REGISTER 24-4: CONFIG2H: CONFIGURATION REGISTER 2 HIGH U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,02
PIC18F/LF1XK50 REGISTER 24-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH R/P-1 U-0 U-0 U-0 R/P-1 U-0 U-0 U-0 MCLRE — — — HFOFST — — — bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ x = Bit is unknown bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled; RA3 input pin disabled 0 = RA3 input pin enabled; MCLR disabled bit 6-4 Unimplemented: Read as ‘0’ bit 3 HFOFST: HFINTOSC Fast Start-up bit 1 = HF
PIC18F/LF1XK50 REGISTER 24-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1 — — — — — — CP1 CP0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-2 Unimplemented: Read as ‘0’ bit 1 CP1: Code Protection bit 1 = Block 1 not code-protected 0 = Block 1 code-protected bit 0 CP0: Code Protection bit 1 = Block 0 not code-protected 0 = Block 0 code-protected REGISTER 2
PIC18F/LF1XK50 REGISTER 24-9: CONFIG6L: CONFIGURATION REGISTER 6 LOW U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1 — — — — — — WRT1 WRT0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-2 Unimplemented: Read as ‘0’ bit 1 WRT1: Write Protection bit 1 = Block 1 not write-protected 0 = Block 1 write-protected bit 0 WRT0: Write Protection bit 1 = Block 0 not write-protected 0 = Block 0 write-protected
PIC18F/LF1XK50 REGISTER 24-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1 — — — — — — EBTR1 EBTR0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-2 Unimplemented: Read as ‘0’ bit 1 EBTR1: Table Read Protection bit 1 = Block 1 not protected from table reads executed in other blocks 0 = Block 1 protected from table reads executed in other blocks bit 0 EBTR0: Ta
PIC18F/LF1XK50 REGISTER 24-13: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F1XK50/PIC18LF1XK50 R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-5 DEV<2:0>: Device ID bits 010 = PIC18F13K50 011 = PIC18F14K50 bit 4-0 REV<4:0>: Revision ID bits These bits are used to indicate the device revision.
PIC18F/LF1XK50 24.2 Watchdog Timer (WDT) For PIC18F/LF1XK50 devices, the WDT is driven by the LFINTOSC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the LFINTOSC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configuration Register 2H. Available periods range from 4 ms to 131.072 seconds (2.18 minutes).
PIC18F/LF1XK50 24.2.1 CONTROL REGISTER Register 24-15 shows the WDTCON register. This is a readable and writable register which contains a control bit that allows software to override the WDT enable Configuration bit, but only if the Configuration bit has disabled the WDT.
PIC18F/LF1XK50 FIGURE 24-2: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F/LF1XK50 Device Address (from/to) 14K50 BBSIZ = 1 0000h 01FFh 13K50 BBSIZ = 0 BBSIZ = 1 BBSIZ = 0 Boot Block, 2 KW Boot Block, 1 KW Boot Block, 1 KW CPB, WRTB, EBTRB CPB, WRTB, EBTRB CPB, WRTB, EBTRB 0200h 03FFh Block 0 3 KW CP0, WRT0, EBTR0 0400h 05FFh 0600h Block 0 1 KW CP0, WRT0, EBTR0 Boot Block, 0.512 KW CPB, WRTB, EBTRB Block 0 1.
PIC18F/LF1XK50 TABLE 24-3: SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L — — — — — — CP1 CP0 300009h CONFIG5H CPD CPB — — — — — — 30000Ah CONFIG6L — — — — — — WRT1 WRT0 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 30000Ch CONFIG7L — — — — — — EBTR1 EBTR0 30000Dh CONFIG7H — EBTRB — — — — — — Legend: Shaded cells are unimplemented. 24.3.
PIC18F/LF1XK50 FIGURE 24-4: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0007FFh 000800h WRTB, EBTRB = 11 TBLPTR = 0008FFh WRT0, EBTR0 = 10 001FFFh 002000h PC = 003FFEh TBLRD* WRT1, EBTR1 = 11 003FFFh 004000h WRT2, EBTR2 = 11 005FFFh 006000h WRT3, EBTR3 = 11 007FFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. TABLAT register returns a value of ‘0’.
PIC18F/LF1XK50 24.3.2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits internal and external writes to data EEPROM. The CPU can always read data EEPROM under normal operation, regardless of the protection bit settings. 24.3.
PIC18F/LF1XK50 NOTES: DS41350E-page 308 Preliminary 2010 Microchip Technology Inc.
PIC18F/LF1XK50 25.0 INSTRUCTION SET SUMMARY PIC18F/LF1XK50 devices incorporate the standard set of 75 PIC18 core instructions, as well as an extended set of 8 new instructions, for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 25.
PIC18F/LF1XK50 TABLE 25-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
PIC18F/LF1XK50 FIGURE 25-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 8 7 OPCODE d a Example Instruction 0 f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 0 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE #) 1111 f =
PIC18F/LF1XK50 TABLE 25-2: PIC18FXXXX INSTRUCTION SET Mnemonic, Operands 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a
PIC18F/LF1XK50 TABLE 25-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG f, b, a f, b, a f, b, a f, b, a f, d, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None 1 (2) 1 (2)
PIC18F/LF1XK50 TABLE 25-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add literal and WREG AND literal with WREG Inclusive OR literal with WREG Move literal (12-bit) 2nd word to FSR(f) 1st word Move literal to BSR<3:0> Move literal to WREG Multiply literal with WREG Return with literal in WREG Subtract WREG fr
PIC18F/LF1XK50 25.1.1 STANDARD INSTRUCTION SET ADDLW ADD literal to W ADDWF ADD W to f Syntax: ADDLW Syntax: ADDWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) + (f) dest Status Affected: N, OV, C, DC, Z k Operands: 0 k 255 Operation: (W) + k W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
PIC18F/LF1XK50 ADDWFC ADD W and CARRY bit to f ANDLW Syntax: ADDWFC Syntax: ANDLW Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 k 255 Operation: (W) .AND. k W Operation: (W) + (f) + (C) dest Status Affected: N, Z Status Affected: N,OV, C, DC, Z Encoding: 0010 Description: f {,d {,a}} Encoding: 00da ffff ffff Add W, the CARRY flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’.
PIC18F/LF1XK50 ANDWF AND W with f BC Branch if Carry Syntax: ANDWF Syntax: BC Operands: 0 f 255 d [0,1] a [0,1] Operands: -128 n 127 Operation: if CARRY bit is ‘1’ (PC) + 2 + 2n PC Status Affected: None f {,d {,a}} Operation: (W) .AND. (f) dest Status Affected: N, Z Encoding: 0001 Description: Encoding: 01da ffff ffff The contents of W are AND’ed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W.
PIC18F/LF1XK50 BCF Bit Clear f BN Branch if Negative Syntax: BCF Syntax: BN Operands: 0 f 255 0b7 a [0,1] Operands: -128 n 127 Operation: if NEGATIVE bit is ‘1’ (PC) + 2 + 2n PC Status Affected: None f, b {,a} Operation: 0 f Status Affected: None Encoding: Encoding: 1001 Description: bbba ffff ffff Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
PIC18F/LF1XK50 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC Syntax: BNN Operands: -128 n 127 Operands: -128 n 127 Operation: if CARRY bit is ‘0’ (PC) + 2 + 2n PC Operation: if NEGATIVE bit is ‘0’ (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: n 1110 Description: 0011 nnnn nnnn Encoding: 1110 If the CARRY bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC.
PIC18F/LF1XK50 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV Syntax: BNZ Operands: -128 n 127 Operands: -128 n 127 Operation: if OVERFLOW bit is ‘0’ (PC) + 2 + 2n PC Operation: if ZERO bit is ‘0’ (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: n 1110 Description: 0101 nnnn nnnn Encoding: 1110 If the OVERFLOW bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC.
PIC18F/LF1XK50 BRA Unconditional Branch BSF Syntax: BRA Syntax: BSF Operands: -1024 n 1023 Operands: 0 f 255 0b7 a [0,1] n Operation: (PC) + 2 + 2n PC Status Affected: None Encoding: 1101 Description: 0nnn nnnn nnnn Add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction.
PIC18F/LF1XK50 BTFSC Bit Test File, Skip if Clear BTFSS Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 f 255 0b7 a [0,1] Operands: 0 f 255 0b<7 a [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Bit Test File, Skip if Set Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped.
PIC18F/LF1XK50 BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV Operands: 0 f 255 0b<7 a [0,1] Operands: -128 n 127 Operation: if OVERFLOW bit is ‘1’ (PC) + 2 + 2n PC Status Affected: None Operation: (f) f Status Affected: None Encoding: 0111 Description: Words: Cycles: Encoding: bbba ffff ffff Bit ‘b’ in data memory location ‘f’ is inverted. If ‘a’ is ‘0’, the Access Bank is selected.
PIC18F/LF1XK50 BZ Branch if Zero CALL Subroutine Call Syntax: BZ Syntax: CALL k {,s} Operands: -128 n 127 Operands: Operation: if ZERO bit is ‘1’ (PC) + 2 + 2n PC 0 k 1048575 s [0,1] Operation: (PC) + 4 TOS, k PC<20:1>, if s = 1 (W) WS, (Status) STATUSS, (BSR) BSRS Status Affected: None Status Affected: n None Encoding: 1110 Description: 0000 nnnn nnnn If the ZERO bit is ‘1’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC.
PIC18F/LF1XK50 CLRF Clear f Syntax: CLRF Operands: 0 f 255 a [0,1] Operation: 000h f 1Z Status Affected: Z Encoding: f {,a} 0110 Description: 101a ffff ffff Clears the contents of the specified register. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.
PIC18F/LF1XK50 COMF Complement f CPFSEQ Compare f with W, skip if f = W Syntax: COMF Syntax: CPFSEQ Operands: 0 f 255 a [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None f {,d {,a}} 0 f 255 d [0,1] a [0,1] Operands: Operation: (f) dest Status Affected: N, Z Encoding: 0001 11da ffff ffff Description: The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W.
PIC18F/LF1XK50 CPFSGT Compare f with W, skip if f > W CPFSLT Compare f with W, skip if f < W Syntax: CPFSGT Syntax: CPFSLT Operands: 0 f 255 a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) –W), skip if (f) > (W) (unsigned comparison) Operation: (f) –W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 Description: Words: f {,a} 010a ffff ffff Compares the contents of data memory location ‘f’ to the contents of the
PIC18F/LF1XK50 DAW Decimal Adjust W Register DECF Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: Operation: If [W<3:0> > 9] or [DC = 1] then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0>; 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest Status Affected: C, DC, N, OV, Z If [W<7:4> + DC > 9] or [C = 1] then (W<7:4>) + 6 + DC W<7:4>; else (W<7:4>) + DC W<7:4> Status Affected: Decrement f Encoding: 0000 0000 0000 0000 DAW adjusts the eight-bit value in W, res
PIC18F/LF1XK50 DECFSZ Decrement f, skip if 0 DCFSNZ Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest, skip if result = 0 Operation: (f) – 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0010 Description: 11da ffff ffff The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W.
PIC18F/LF1XK50 GOTO Unconditional Branch INCF Syntax: GOTO k Syntax: INCF Operands: 0 k 1048575 Operands: Operation: k PC<20:1> 0 f 255 d [0,1] a [0,1] Status Affected: None Operation: (f) + 1 dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 Description: 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 GOTO allows an unconditional branch Increment f Encoding: 0010 2 Cycles: 2 Q1 Q2 Q3 Q4 Read literal ‘k’<7:0>, No operation R
PIC18F/LF1XK50 INCFSZ Increment f, skip if 0 INFSNZ Syntax: INCFSZ Syntax: INFSNZ 0 f 255 d [0,1] a [0,1] f {,d {,a}} Increment f, skip if not 0 f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: Operation: (f) + 1 dest, skip if result = 0 Operation: (f) + 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0011 Description: 11da ffff ffff The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in W.
PIC18F/LF1XK50 IORLW Inclusive OR literal with W IORWF Syntax: IORLW k Syntax: IORWF Operands: 0 k 255 Operands: Operation: (W) .OR. k W 0 f 255 d [0,1] a [0,1] Status Affected: N, Z Operation: (W) .OR. (f) dest Status Affected: N, Z Encoding: 0000 Description: 1001 kkkk kkkk The contents of W are ORed with the eight-bit literal ‘k’. The result is placed in W.
PIC18F/LF1XK50 LFSR Load FSR MOVF Syntax: LFSR f, k Syntax: MOVF Operands: 0f2 0 k 4095 Operands: Operation: k FSRf 0 f 255 d [0,1] a [0,1] Status Affected: None Operation: f dest Status Affected: N, Z Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the File Select Register pointed to by ‘f’.
PIC18F/LF1XK50 MOVFF Move f to f MOVLB Syntax: MOVFF fs,fd Syntax: MOVLW k Operands: 0 fs 4095 0 fd 4095 Operands: 0 k 255 Operation: k BSR Operation: (fs) fd Status Affected: None Status Affected: None Encoding: Encoding: 1st word (source) 2nd word (destin.) 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register ‘fs’ are moved to destination register ‘fd’.
PIC18F/LF1XK50 MOVLW Move literal to W MOVWF Syntax: MOVLW k Syntax: MOVWF Operands: 0 k 255 Operands: Operation: kW 0 f 255 a [0,1] Status Affected: None Operation: (W) f Status Affected: None Encoding: 0000 1110 kkkk kkkk Description: The eight-bit literal ‘k’ is loaded into W. Words: 1 Cycles: 1 Move W to f Encoding: 0110 Q1 Q2 Q3 Q4 Read literal ‘k’ Process Data Write to W Example: MOVLW = ffff ffff Move data from W to register ‘f’.
PIC18F/LF1XK50 MULLW Multiply literal with W MULWF Multiply W with f Syntax: MULLW Syntax: MULWF Operands: 0 k 255 Operands: Operation: (W) x k PRODH:PRODL 0 f 255 a [0,1] Status Affected: None Operation: (W) x (f) PRODH:PRODL Status Affected: None Encoding: 0000 Description: k 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in the PRODH:PRODL register pair.
PIC18F/LF1XK50 NEGF Negate f NOP No Operation Syntax: NEGF Syntax: NOP Operands: 0 f 255 a [0,1] Operands: None Operation: (f)+1f Status Affected: N, OV, C, DC, Z Encoding: f {,a} 0110 Description: 1 Cycles: 1 No operation Status Affected: None Encoding: 110a ffff 0000 1111 ffff Location ‘f’ is negated using two’s complement. The result is placed in the data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected.
PIC18F/LF1XK50 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) bit bucket Operation: (PC + 2) TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
PIC18F/LF1XK50 RCALL Relative Call RESET Reset Syntax: RCALL Syntax: RESET Operands: -1024 n 1023 Operands: None Operation: (PC) + 2 TOS, (PC) + 2 + 2n PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: n 1101 Description: 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack.
PIC18F/LF1XK50 RETFIE Return from Interrupt RETLW Return literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s [0,1] Operands: 0 k 255 Operation: (TOS) PC, 1 GIE/GIEH or PEIE/GIEL, if s = 1 (WS) W, (STATUSS) Status, (BSRS) BSR, PCLATU, PCLATH are unchanged.
PIC18F/LF1XK50 RETURN Return from Subroutine RLCF Syntax: RETURN {s} Syntax: RLCF Operands: s [0,1] Operands: Operation: (TOS) PC, if s = 1 (WS) W, (STATUSS) Status, (BSRS) BSR, PCLATU, PCLATH are unchanged 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) C, (C) dest<0> Status Affected: C, N, Z Status Affected: None Encoding: 0000 Rotate Left f through Carry Encoding: 0000 0001 001s Description: Return from subroutine.
PIC18F/LF1XK50 RLNCF Rotate Left f (No Carry) RRCF Syntax: RLNCF Syntax: RRCF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) dest<0> Operation: Status Affected: N, Z (f) dest, (f<0>) C, (C) dest<7> Status Affected: C, N, Z Encoding: 0100 Description: f {,d {,a}} 01da ffff ffff The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result is placed in W.
PIC18F/LF1XK50 RRNCF Rotate Right f (No Carry) SETF Syntax: RRNCF Syntax: SETF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 a [0,1] Operation: FFh f Operation: (f) dest, (f<0>) dest<7> Status Affected: None Status Affected: f {,d {,a}} Encoding: N, Z Encoding: 0100 Description: 00da ffff ffff The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W.
PIC18F/LF1XK50 SLEEP Enter Sleep mode SUBFWB Syntax: SLEEP Syntax: SUBFWB Operands: None Operands: Operation: 00h WDT, 0 WDT postscaler, 1 TO, 0 PD 0 f 255 d [0,1] a [0,1] Operation: (W) – (f) – (C) dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Encoding: 0000 0000 0011 Description: The Power-down Status bit (PD) is cleared. The Time-out Status bit (TO) is set. Watchdog Timer and its postscaler are cleared.
PIC18F/LF1XK50 SUBLW Subtract W from literal SUBWF Syntax: SUBLW k Syntax: SUBWF Operands: 0 k 255 Operands: Operation: k – (W) W 0 f 255 d [0,1] a [0,1] Status Affected: N, OV, C, DC, Z Operation: (f) – (W) dest Status Affected: N, OV, C, DC, Z Encoding: 0000 Description 1000 kkkk kkkk W is subtracted from the eight-bit literal ‘k’. The result is placed in W.
PIC18F/LF1XK50 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB Syntax: SWAPF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – (W) – (C) dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> Status Affected: None Encoding: 0101 Description: f {,d {,a}} 10da ffff ffff Subtract W and the CARRY flag (borrow) from register ‘f’ (2’s complement method).
PIC18F/LF1XK50 TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) TABLAT; TBLPTR – No Change; if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) + 1 TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) – 1 TBLPTR; if TBLRD +*, (TBLPTR) + 1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT; Example2: 0000 0000 0000 TBLRD = = = 55h 00A356h 34h = = 34h 00A357h +* ; Before Instruction TAB
PIC18F/LF1XK50 TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example1: TBLWT *+; Operands: None Operation: if TBLWT*, (TABLAT) Holding Register; TBLPTR – No Change; if TBLWT*+, (TABLAT) Holding Register; (TBLPTR) + 1 TBLPTR; if TBLWT*-, (TABLAT) Holding Register; (TBLPTR) – 1 TBLPTR; if TBLWT+*, (TBLPTR) + 1 TBLPTR; (TABLAT) Holding Register; Status Affected: Before Instruction TABLAT = 55h TBLPTR = 00A356h HOLDING REGISTER (00A356h) = FFh After In
PIC18F/LF1XK50 TSTFSZ Test f, skip if 0 XORLW Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 f 255 a [0,1] Operands: 0 k 255 Operation: (W) .XOR. k W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: Encoding: 0110 Description: Exclusive OR literal with W 011a ffff ffff If ‘f’ = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction.
PIC18F/LF1XK50 XORWF Exclusive OR W with f Syntax: XORWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 f {,d {,a}} 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
PIC18F/LF1XK50 25.2 Extended Instruction Set A summary of the instructions in the extended instruction set is provided in Table 25-3. Detailed descriptions are provided in Section 25.2.2 “Extended Instruction Set”. The opcode field descriptions in Table 25-1 (page 310) apply to both the standard and extended PIC18 instruction sets. In addition to the standard 75 instructions of the PIC18 instruction set, PIC18F/LF1XK50 devices also provide an optional extension to the core CPU functionality.
PIC18F/LF1XK50 25.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 k 63 f [ 0, 1, 2 ] Operands: 0 k 63 Operation: FSR(f) + k FSR(f) Status Affected: None Encoding: 1110 Add Literal to FSR2 and Return FSR2 + k FSR2, Operation: (TOS) PC Status Affected: 1000 ffkk kkkk Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’.
PIC18F/LF1XK50 CALLW Subroutine Call Using WREG MOVSF Syntax: CALLW Syntax: MOVSF [zs], fd Operands: None Operands: Operation: (PC + 2) TOS, (W) PCL, (PCLATH) PCH, (PCLATU) PCU 0 zs 127 0 fd 4095 Operation: ((FSR2) + zs) fd Status Affected: None Status Affected: None Encoding: 0000 0000 0001 0100 Description First, the return address (PC + 2) is pushed onto the return stack. Next, the contents of W are written to PCL; the existing value is discarded.
PIC18F/LF1XK50 MOVSS Move Indexed to Indexed PUSHL Syntax: Syntax: PUSHL k Operands: MOVSS [zs], [zd] 0 zs 127 0 zd 127 Operands: 0k 255 Operation: ((FSR2) + zs) ((FSR2) + zd) Operation: k (FSR2), FSR2 – 1 FSR2 Status Affected: None Status Affected: None Encoding: 1st word (source) 2nd word (dest.) 1110 1111 Description 1011 xxxx 1zzz xzzz zzzzs zzzzd The contents of the source register are moved to the destination register.
PIC18F/LF1XK50 SUBFSR Subtract Literal from FSR SUBULNK Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 k 63 Operands: 0 k 63 f [ 0, 1, 2 ] Operation: Operation: FSR(f) – k FSRf Status Affected: None Encoding: 1110 FSR2 – k FSR2 (TOS) PC Status Affected: None 1001 ffkk kkkk Description: The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘f’.
PIC18F/LF1XK50 25.2.3 Note: BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing mode (Section 3.5.1 “Indexed Addressing with Literal Offset”).
PIC18F/LF1XK50 ADDWF ADD W to Indexed (Indexed Literal Offset mode) BSF Bit Set Indexed (Indexed Literal Offset mode) Syntax: ADDWF Syntax: BSF [k], b Operands: 0 k 95 d [0,1] Operands: 0 f 95 0b7 Operation: (W) + ((FSR2) + k) dest Operation: 1 ((FSR2) + k) Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: [k] {,d} 0010 Description: 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offset by the value ‘k
PIC18F/LF1XK50 25.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB® IDE TOOLS The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set of the PIC18F/LF1XK50 family of devices. This includes the MPLAB® C18 C compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device.
PIC18F1XK50/PIC18LF1XK50 26.0 DEVELOPMENT SUPPORT 26.
PIC18F1XK50/PIC18LF1XK50 26.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
PIC18F1XK50/PIC18LF1XK50 26.7 MPLAB SIM Software Simulator 26.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC18F1XK50/PIC18LF1XK50 26.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 26.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC18F/LF1XK50 27.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias....................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS, PIC18F1XK50 .......................................................................... -0.
PIC18F/LF1XK50 27.1 DC Characteristics: PIC18F/LF1XK50-I/E (Industrial, Extended) PIC18LF1XK50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC18F1XK50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param. No. D001 Sym VDD Characteristic VDR D004* Max Units Conditions PIC18LF1XK50 1.8 2.7 — — 3.
PIC18F/LF1XK50 FIGURE 27-1: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR POR REARM VSS TVLOW(2) Note 1: 2: 3: TPOR(3) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. 2010 Microchip Technology Inc.
PIC18F/LF1XK50 27.2 DC Characteristics: PIC18F/LF1XK50-I/E (Industrial, Extended) PIC18LF1XK50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC18F1XK50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC18F/LF1XK50 27.2 DC Characteristics: PIC18F/LF1XK50-I/E (Industrial, Extended) (Continued) PIC18LF1XK50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC18F1XK50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC18F/LF1XK50 27.2 DC Characteristics: PIC18F/LF1XK50-I/E (Industrial, Extended) (Continued) PIC18LF1XK50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC18F1XK50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC18F/LF1XK50 27.2 DC Characteristics: PIC18F/LF1XK50-I/E (Industrial, Extended) (Continued) PIC18LF1XK50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC18F1XK50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC18F/LF1XK50 27.2 DC Characteristics: PIC18F/LF1XK50-I/E (Industrial, Extended) (Continued) PIC18LF1XK50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC18F1XK50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC18F/LF1XK50 27.2 DC Characteristics: PIC18F/LF1XK50-I/E (Industrial, Extended) (Continued) PIC18LF1XK50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC18F1XK50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC18F/LF1XK50 27.3 DC Characteristics: PIC18F/LF1XK50-I/E (Power-Down) PIC18LF1XK50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC18F1XK50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC18F/LF1XK50 27.3 DC Characteristics: PIC18F/LF1XK50-I/E (Power-Down) (Continued) PIC18LF1XK50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC18F1XK50 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC18F/LF1XK50 27.4 DC Characteristics: PIC18F/LF1XK50-I/E DC CHARACTERISTICS Param No. Sym VIL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Min Typ† Max Units — — with Schmitt Trigger buffer with I2C levels Conditions — 0.8 V 4.5V VDD 5.5V — 0.15 VDD V 1.8V VDD 4.5V — — 0.2 VDD V 1.8V VDD 5.5V — — 0.
PIC18F/LF1XK50 27.4 DC Characteristics: PIC18F/LF1XK50-I/E (Continued) DC CHARACTERISTICS Param No. Sym Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Min Typ† Max Units Conditions — — 15 pF — — 50 pF Cell Endurance 10K 100K — — E/W VDD for Read VMIN — — V Voltage on MCLR/VPP during Erase/Program 8.0 — 9.
PIC18F/LF1XK50 27.5 USB Module Specifications Operating Conditions-40°C TA +85°C (unless otherwise state) Param No. Sym Characteristic Min Typ Max Units Conditions D313 VUSB USB Voltage 3.0 — 3.6 V D314 IIL Input Leakage on pin — — ±1 A D315 — — 0.8 V 2.
PIC18F/LF1XK50 27.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. TH01 TH02 TH03 TH04 TH05 Sym Characteristic JA Thermal Resistance Junction to Ambient JC TJMAX PD Thermal Resistance Junction to Case Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation Typ Units Conditions 62.4 C/W 20-pin PDIP package 85.2 C/W 20-pin SOIC package 108.
PIC18F/LF1XK50 27.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC18F/LF1XK50 27.8 AC Characteristics: PIC18F1XK50/PIC18LF1XK50-I/E FIGURE 27-3: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) PIC18F1XK50 VOLTAGE FREQUENCY GRAPH, -40°C TA +85°C FIGURE 27-4: 5.5 VDD (V) 3.6 2.7 1.8 0 10 20 40 48 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 27-1 for each Oscillator mode’s supported frequencies.
PIC18F/LF1XK50 PIC18LF1XK50 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C FIGURE 27-5: VDD (V) 3.6 2.7 1.8 0 10 20 40 48 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 27-1 for each Oscillator mode’s supported frequencies. HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE FIGURE 27-6: 125 ± 5% Temperature (°C) 85 ± 3% 60 ± 2% ± 5% 25 0 ± 5% -20 -40 1.8 2.0 2.5 3.0 3.3(2) 3.5 4.0 4.5 5.0 5.
PIC18F/LF1XK50 TABLE 27-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. OS01 Sym FOSC Characteristic External CLKIN Frequency(1) Oscillator Frequency(1) OS02 TOSC External CLKIN Period(1) Oscillator Period(1) Min Typ† Max Units Conditions DC — 37 kHz DC — 4 MHz EC Oscillator mode (medium) DC — 48 MHz EC Oscillator mode (high) EC Oscillator mode (low) — 32.
PIC18F/LF1XK50 TABLE 27-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym Characteristic OS08 HFOSC OS10* TIOSC ST HFINTOSC Wake-up from Sleep Start-up Time Internal Calibrated HFINTOSC Frequency(2) Freq. Tolerance Min Typ† Max Units 2% 3% — — 16.0 16.0 — — MHz MHz 5% — 16.0 — MHz — — 5 8 s VDD = 2.0V, -40°C to +85°C — — 5 8 s VDD = 3.0V, -40°C to +85°C — — 5 8 s VDD = 5.
PIC18F/LF1XK50 FIGURE 27-7: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 27-4: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No.
PIC18F/LF1XK50 FIGURE 27-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 31/ 31A 34 34 I/O pins Note 1: Asserted low.
PIC18F/LF1XK50 TABLE 27-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym Characteristic Min Typ† Max Units Conditions 30 TMCL MCLR Pulse Width (low) 2 5 — — — — s s VDD = 3.3-5V, -40°C to +85°C VDD = 3.3-5V 31 TWDT Standard Watchdog Timer Time-out Period(5) 10 10 17 17 27 30 ms ms VDD = 3.3V-5V, -40°C to +85°C VDD = 3.
PIC18F/LF1XK50 FIGURE 27-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 27-6: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No.
PIC18F/LF1XK50 FIGURE 27-11: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCPx (Capture mode) CC01 CC02 CC03 Note: Refer to Figure 27-2 for load conditions. TABLE 27-7: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym Characteristic CC01* TccL CCPx Input Low Time CC02* TccH CCPx Input High Time CC03* TccP * † Min Typ† Max Units 0.5TCY + 20 — — ns With Prescaler 20 — — ns No Prescaler 0.
PIC18F/LF1XK50 FIGURE 27-12: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 132 A/D CLK 9 A/D DATA 8 7 .. . ... 2 1 0 NEW_DATA OLD_DATA ADRES TCY ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
PIC18F/LF1XK50 TABLE 27-10: COMPARATOR SPECIFICATIONS Operating Conditions: 1.8V < VDD < 3.6V, -40°C < TA < +125°C (unless otherwise stated). Param No. Sym Characteristics Input Offset Voltage Min Typ Max Units Comments — — ±7.
PIC18F/LF1XK50 FIGURE 27-13: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US122 US120 Note: Refer to Figure 27-2 for load conditions. TABLE 27-13: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param. No. Symbol Characteristic Min. Max. Units US120 TCKH2DTV SYNC XMIT (Master and Slave) Clock high to data-out valid 3.0-5.5V — 80 ns 1.8-5.
PIC18F/LF1XK50 FIGURE 27-15: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS SP70 SCK (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDO LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 27-2 for load conditions.
PIC18F/LF1XK50 FIGURE 27-17: SPI SLAVE MODE TIMING (CKE = 0) SS SP70 SCK (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 MSb SDO LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 27-2 for load conditions.
PIC18F/LF1XK50 TABLE 27-15: SPI MODE REQUIREMENTS Param No.
PIC18F/LF1XK50 TABLE 27-16: I2C™ BUS START/STOP BITS REQUIREMENTS Param No.
PIC18F/LF1XK50 TABLE 27-17: I2C™ BUS DATA REQUIREMENTS Param. No. Symbol SP100* THIGH Characteristic Clock high time Min Max Units 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1.5TCY — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.
PIC18F/LF1XK50 NOTES: DS41350E-page 396 Preliminary 2010 Microchip Technology Inc.
PIC18F/LF1XK50 28.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs and tables are not available at this time. 2010 Microchip Technology Inc.
PIC18F/LF1XK50 NOTES: DS41350E-page 398 Preliminary 2010 Microchip Technology Inc.
PIC18F/LF1XK50 29.0 PACKAGING INFORMATION 29.1 Package Marking Information 20-Lead PDIP Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN PICXXFXXXX-I/P 0810017 20-Lead SSOP Example XXXXXXXXXXX XXXXXXXXXXX YYWWNNN PICXXFXXXX -I/SS 0810017 20-Lead SOIC (.300”) Example XXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX PICXXFXXXX-I /SO 0810017 YYWWNNN 20-Lead QFN Example XXXXXXX XXXXXXX YYWWNNN Legend: XX...
PIC18F/LF1XK50 29.2 Package Details The following sections give the technical details of the packages.
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PIC18F/LF1XK50 20-Lead Plastic Quad Flat, No Lead Package (MQ) 5x5x0.9 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-120A 2010 Microchip Technology Inc.
PIC18F/LF1XK50 NOTES: DS41350E-page 404 Preliminary 2010 Microchip Technology Inc.
PIC18F/LF1XK50 APPENDIX A: REVISION HISTORY Revision A (May 2008) Original data sheet for PIC18F1XK50/PIC18LF1XK50 devices. Revision B (June 2008) Revised 27.4 DC Characteristics table. Revision C (04/2009) Revised data sheet title; Revised Features section; Revised Table 1-2; Revised Table 3-1, Table 3-2; Added Note 3 in Section 9.1; Revised Register 14-1; Revised Example 16-1; Revised Section 18.8.4; Revised Register 18-3; Revised Table 20-2; Revised Sections 22.2.1, 22.2.2, 22.5.1.1, 22.
PIC18F/LF1XK50 APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1.
PIC18F/LF1XK50 INDEX A A/D Analog Port Pins, Configuring .................................. 221 Associated Registers ............................................... 221 Conversions ............................................................. 212 Discharge ................................................................. 213 Selecting and Configuring Acquisition Time ............ 210 Specifications ........................................................... 387 Absolute Maximum Ratings .....................
PIC18F/LF1XK50 C C Compilers MPLAB C18 ............................................................. 360 CALL ................................................................................ 324 CALLW ............................................................................. 353 Capture (CCP Module) ..................................................... 119 CCP Pin Configuration ............................................. 119 CCPRxH:CCPRxL Registers ................................... 119 Prescaler ....
PIC18F/LF1XK50 Graphs and Tables .................................................. 397 DC Characteristics Extended and Industrial ........................................... 374 Industrial and Extended ........................................... 364 DCFSNZ .......................................................................... 329 DECF ............................................................................... 328 DECFSZ ...........................................................................
PIC18F/LF1XK50 H Hardware Multiplier ............................................................ 65 Introduction ................................................................ 65 Operation ................................................................... 65 Performance Comparison .......................................... 65 I I/O Ports ............................................................................. 83 I2C Associated Registers ...............................................
PIC18F/LF1XK50 TBLRD ..................................................................... 347 TBLWT ..................................................................... 348 TSTFSZ ................................................................... 349 XORLW .................................................................... 349 XORWF .................................................................... 350 INTCON Register ...............................................................
PIC18F/LF1XK50 and SPI Operation ................................................... 147 Entering .................................................................... 235 Exiting Idle and Sleep Modes .................................. 239 by Interrupt ....................................................... 239 by Reset ........................................................... 240 by WDT Time-out ............................................. 239 Without a Start-up Delay ..................................
PIC18F/LF1XK50 REFCON0 ................................................................ 247 REFCON1 ................................................................ 248 REFCON2 ................................................................ 248 SLRCON (PORT Slew Rate Control) ....................... 100 SRCON0 (SR Latch Control 0) ................................ 242 SRCON1 (SR Latch Control 1) ................................ 243 SSPADD (MSSP Address and Baud Rate, SPI Mode) ..
PIC18F/LF1XK50 Time-out in Various Situations (table) .............................. 281 Timer0 .............................................................................. 101 Associated Registers ............................................... 103 Operation ................................................................. 102 Overflow Interrupt .................................................... 103 Prescaler ..................................................................
PIC18F/LF1XK50 I2C Bus Start/Stop Bits ............................................ 394 SPI Mode ................................................................. 393 Top-of-Stack Access .......................................................... 30 TRISA Register .................................................................. 85 TRISB Register ............................................................ 90, 94 TSTFSZ ...........................................................................
PIC18F/LF1XK50 NOTES: DS41350E-page 416 Preliminary 2010 Microchip Technology Inc.
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