Datasheet

PIC18(L)F1XK22
DS41365E-page 398  2009-2011 Microchip Technology Inc.
Interrupt..................................................................... 106
Operation ..................................................................105
Output ....................................................................... 106
Timer3............................................................................... 107
16-Bit Read/Write Mode............................................ 110
Associated Registers ................................................ 110
Operation ..................................................................108
Oscillator ........................................................... 107, 110
Overflow Interrupt ............................................. 107, 110
Special Event Trigger (CCP)..................................... 110
TMR3H Register ....................................................... 107
TMR3L Register........................................................107
Timing Diagrams
A/D Conversion......................................................... 354
Acknowledge Sequence ........................................... 168
Asynchronous Reception .......................................... 182
Asynchronous Transmission ..................................... 178
Asynchronous Transmission (Back to Back) ............ 179
Auto Wake-up Bit (WUE) During Normal Operation . 193
Auto Wake-up Bit (WUE) During Sleep .................... 193
Automatic Baud Rate Calculator............................... 191
Baud Rate Generator with Clock Arbitration ............. 162
BRG Reset Due to SDA Arbitration During Start
Condition........................................................... 171
Brown-out Reset (BOR) ............................................ 350
Bus Collision During a Repeated Start Condition
(Case 1) ............................................................172
Bus Collision During a Repeated Start Condition
(Case 2) ............................................................172
Bus Collision During a Start Condition (SCL = 0) ..... 171
Bus Collision During a Stop Condition (Case 1) ....... 173
Bus Collision During a Stop Condition (Case 2) ....... 173
Bus Collision During Start Condition (SDA only) ...... 170
Bus Collision for Transmit and Acknowledge............ 169
CLKOUT and I/O....................................................... 349
Clock Synchronization .............................................. 155
Clock Timing ............................................................. 346
Clock/Instruction Cycle ............................................... 29
Comparator Output ...................................................217
Enhanced Capture/Compare/PWM (ECCP) ............. 353
Fail-Safe Clock Monitor (FSCM) ................................. 24
First Start Bit Timing .................................................163
Full-Bridge PWM Output ........................................... 120
Half-Bridge PWM Output .................................. 118, 126
I
2
C Bus Data.............................................................360
I
2
C Bus Start/Stop Bits.............................................. 359
I
2
C Master Mode (7 or 10-Bit Transmission) ............ 166
I
2
C Master Mode (7-Bit Reception) ........................... 167
I
2
C Slave Mode (10-Bit Reception, SEN = 0) ........... 150
I
2
C Slave Mode (10-Bit Reception, SEN = 1) ........... 157
I
2
C Slave Mode (10-Bit Transmission)...................... 151
I
2
C Slave Mode (7-bit Reception, SEN = 0).............. 148
I
2
C Slave Mode (7-Bit Reception, SEN = 1) ............. 156
I
2
C Slave Mode (7-Bit Transmission)........................ 149
I
2
C Slave Mode General Call Address Sequence (7 or
10-Bit Address Mode) ....................................... 158
I
2
C Stop Condition Receive or Transmit Mode ......... 168
Internal Oscillator Switch Timing................................. 21
PWM Auto-shutdown
Auto-restart Enabled ......................................... 125
Firmware Restart .............................................. 124
PWM Direction Change ............................................ 121
PWM Direction Change at Near 100% Duty Cycle ... 122
PWM Output (Active-High)........................................ 116
PWM Output (Active-Low) ........................................ 117
Repeat Start Condition ............................................. 164
Reset, WDT, OST and Power-up Timer ................... 350
Send Break Character Sequence............................. 194
Slave Synchronization .............................................. 139
Slow Rise Time (MCLR
Tied to VDD,
V
DD Rise > TPWRT) ........................................... 251
SPI Master Mode (CKE = 1, SMP = 1) ..................... 357
SPI Mode (Master Mode).......................................... 138
SPI Mode (Slave Mode, CKE = 0) ............................ 140
SPI Mode (Slave Mode, CKE = 1) ............................ 140
SPI Slave Mode (CKE = 0) ....................................... 358
SPI Slave Mode (CKE = 1) ....................................... 358
Synchronous Reception (Master Mode, SREN) ....... 198
Synchronous Transmission ...................................... 196
Synchronous Transmission (Through TXEN) ........... 196
Time-out Sequence on POR w/PLL Enabled
(MCLR
Tied to VDD) ........................................ 251
Time-out Sequence on Power-up (MCLR
Not Tied to V
DD, Case 1) .................................. 250
Time-out Sequence on Power-up (MCLR
Not Tied to V
DD, Case 2) .................................. 250
Time-out Sequence on Power-up (MCLR
Tied to V
DD, VDD Rise < TPWRT) ...................... 250
Timer0 and Timer1 External Clock ........................... 352
Transition for Entry to Sleep Mode ........................... 231
Transition for Wake from Sleep (HSPLL) ................. 231
Transition Timing for Entry to Idle Mode................... 232
Transition Timing for Wake from Idle to Run Mode .. 232
USART Synchronous Receive (Master/Slave) ......... 356
USART Synchronous Transmission (Master/Slave). 356
Timing Diagrams and Specifications
A/D Conversion Requirements ................................. 354
External Clock Requirements ................................... 347
PLL Clock ................................................................. 348
Timing Parameter Symbology .......................................... 345
Timing Requirements
I
2
C Bus Data............................................................. 361
I2C Bus Start/Stop Bits............................................. 360
SPI Mode .................................................................. 359
Top-of-Stack Access........................................................... 26
TRISA Register................................................................... 79
TRISB Register............................................................. 84, 88
TSTFSZ ............................................................................ 313
Two-Speed Start-up.......................................................... 257
Two-Word Instructions
Example Cases........................................................... 30
TXREG ............................................................................. 177
TXSTA Register................................................................ 184
BRGH Bit .................................................................. 187
U
USART
Synchronous Master Mode
Requirements, Synchronous Receive .............. 356
Requirements, Synchronous Transmission...... 356
Timing Diagram, Synchronous Receive ........... 356
Timing Diagram, Synchronous Transmission... 356
V
Voltage Reference (VR)
Specifications ........................................................... 355
Voltage Reference. See Comparator Voltage
Reference (CV
REF)
Voltage References
Fixed Voltage Reference (FVR)................................ 240
VR Stabilization ........................................................ 240