Information
2009-2011 Microchip Technology Inc. DS80437F-page 7
PIC18(L)F1XK22
4.6 First SPI High Time Short
In SPI Master mode, when the SPI clock is
configured for Timer2/2 (SSPCON1
<3:0> = 0011), the first SPI high time may
be short.
Work around
Option 1: Ensure TMR2 value rolls over to
zero immediately before writing to
SSPBUF.
Option 2: Turn Timer2 off and clear TMR2
before writing SSPBUF. Enable
TMR2 after SSPBUF is written.
Affected Silicon Revisions
4.7 Incorrect 9
th
Pulse Generated on SCK
In any SPI Master mode, SCK = TMR2/2, if
SSPBUF is written to while shifting out data,
a ninth SCK pulse is incorrectly generated.
At that point, the module locks the user from
writing to the SSPBUF register, but a write
attempt will still cause 8 or 9 more SCK
pulses to be generated.
Work around
The WCOL bit of the SSPCON register is
correctly set to indicate that there was a write
collision. Any time this bit is set, the module
must be disabled and enabled (toggle
SSPEN) to return to the correct operation.
The bus will remain out of synchronization.
Affected Silicon Revisions.
5. Module: In-Circuit Serial Programming™
(ICSP™)
5.1 Minimum VDD for ICSP™
The device cannot be programmed using
ICSP when the device VDD is less than 2.0V.
Work around
Ensure that the device voltage is 2.0V or
higher when programming the device.
Affected Silicon Revisions
6. Module: Oscillator
6.1 Clock Switching
When the FCMEN Configuration bit is set
and the IESO Configuration bit is not set,
then a clock failure during Sleep will not be
detected.
Work around
The IESO Configuration bit must also be set
when the FCMEN Configuration bit is set.
Affected Silicon Revisions
7. Module: Interrupt-on-Change
7.1 Interrupt-on-Change
Setting a PORTB interrupt-on-change
enable bit of the IOCB register while the cor-
responding PORTB input is high will cause
an RBIF interrupt.
Work around
Set the IOCB bits to the desired configura-
tion, then read PORTB to clear the mismatch
latches. Finally, clear the RBIF bit before set-
ting the RBIE bit.
Affected Silicon Revisions
A3 A7 A8 AA
XXX
X
A3 A7 A8 AA
XXX
X
A3 A7 A8 AA
XXX
X
A3 A7 A8 AA
XXX
X
A3 A7 A8
AA
XXX
X