Information

PIC18(L)F1XK22
DS80437F-page 6  2009-2011 Microchip Technology Inc.
3.4 Unexpected Results
Unexpected results occur if the EUSART is
disabled and then re-enabled with the
EUSART receive interrupt and global inter-
rupts enabled, then a single-cycle instruction
is followed by a two cycle instruction.
Work around
Always execute at least two single-cycle
instructions, immediately following setting
the SPEN bit to ‘1’.
Affected Silicon Revisions
4. Module: MSSP (Master Synchronous
Serial Port)
4.1 Baud Rate Error When SSPADD = 0x03
In I
2
C™ Master mode, baud rates obtained
by setting SSPADD to a value less than
0x03 will cause unexpected operation.
Work around
Ensure SSPADD is set to a value greater
than or equal to 0x03.
Affected Silicon Revisions
4.2 SDI Pin Incorrectly Sampled
In SPI Master mode, when the CKE bit is
cleared and the SMP bit is set, the last bit of
the incoming data stream (bit 0) at the SDI
pin will not be sampled properly.
Work around
None.
Affected Silicon Revisions
4.3 SCK Pin Unexpected Pulse
When SPI is enabled in Master mode with
CKE = 1 and CKP = 0, a 1/F
OSC wide pulse
will occur on the SCK pin.
Work around
Configure the SCK pin as an input until after
the MSSP is setup.
Affected Silicon Revisions
4.4 SSPADD Invalid Values
In I
2
C Master mode, SSPADD values of
0x00, 0x01, 0x02 are invalid. The current I
2
C
Baud Rate Generator (BRG) is not set up to
generate a clock signal for these values.
Work around
None.
Affected Silicon Revisions
4.5 RCEN Bit Not Cleared Correctly
In I
2
C Master mode, the RCEN bit is not
cleared by hardware if improper Stop is
received on the bus.
Work around
Reset the module via clearing and setting
the SSPEN bit of SSPCON1.
Affected Silicon Revisions
A3 A7 A8 AA
XXX
X
A3 A7 A8
AA
XXX
X
A3 A7 A8
AA
XXX
X
A3 A7 A8 AA
XXX
X
A3 A7 A8
AA
XXX
X
A3 A7 A8
AA
XXX
X