Information

 2009-2011 Microchip Technology Inc. DS80437F-page 3
PIC18(L)F1XK22
Silicon Errata Issues
1. Module: ADC (Analog-to-Digital
Converter)
1.1 Large INL Error on AN3
ADC conversion on AN3/OSC2 will have
large INL error up to approximately 8 LSb.
Work around
None for the AN3 pin. For better accuracy,
use another analog pin.
Affected Silicon Revisions
1.2 ADC Conversion Does Not Complete
An ADC conversion may not complete under
these conditions:
1. When F
OSC is greater than 8 MHz and is
the clock source used for the ADC
converter.
2. The ADC is operating from its dedicated
internal FRC oscillator and the device is
not in Sleep mode (an F
OSC frequency).
When this occurs, the ADC Interrupt
Flag (ADIF) does not get set, the GO/
DONE
bit does not get cleared, and the
conversion result does not get loaded
into the ADRESH and ADRESL result
registers.
Work around
Method 1: Select the system clock, FOSC,
as the ADC clock source and
reduce the F
OSC frequency to 8
MHz or less when performing
ADC conversions.
Method 2: Select the dedicated FRC
oscillator as the ADC
conversion clock source and
perform all conversions with the
device in Sleep.
Method 3: Method 3 is provided if the
application cannot use Sleep
mode and requires continuous
operation at frequencies above
8 MHz. This method requires
early termination of an ADC
conversion. Provide a fixed time
delay in software to stop the A-
to-D conversion manually, after
all 10 bits are converted, but
before the conversion would
complete automatically. The
conversion is stopped by
clearing the GO/DONE
bit in
software. The GO/DONE
bit
must be cleared during the last
½ TAD cycle, before the
conversion would have
completed automatically. Refer
to Figure 1 for details.
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (AA).
A3 A7 A8
AA
XXX
X