Datasheet

PIC18F1230/1330
DS39758D-page 94  2009 Microchip Technology Inc.
FIGURE 11-1: PIC18 INTERRUPT LOGIC
RBIE
GIE/GIEH
PEIE/GIEL
Wake-up if in
Interrupt to CPU
Vector to Location
0008h
INT2IF
INT2IE
INT2IP
INT1IF
INT1IE
INT1IP
TMR0IF
TMR0IE
TMR0IP
RBIF
RBIE
RBIP
IPEN
RBIF
RBIP
INT2IF
INT2IE
INT2IP
INT0IF
INT0IE
INT1IF
INT1IE
PEIE/GIEL
Interrupt to CPU
Vector to Location
IPEN
IPEN
0018h
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
ADIF
ADIE
ADIP
PTIF
PTIE
PTIP
Additional Peripheral Interrupts
ADIF
ADIE
ADIP
High-Priority Interrupt Generation
Low-Priority Interrupt Generation
PTIF
PTIE
PTIP
Additional Peripheral Interrupts
Idle or Sleep modes
GIE/GIEH
TMR0IE
TMR0IF
TMR0IP
INT1IP
From Power Control PWM
Interrupt Logic
From Power Control
PWM Interrupt Logic