Datasheet

PIC18F1230/1330
 2009 Microchip Technology Inc. DS39758D-page 61
TABLE 6-2: REGISTER FILE SUMMARY (PIC18F1230/1330)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on
Page:
TOSU
— — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 47, 52
TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 47, 52
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 47, 52
STKPTR STKFUL
(5)
STKUNF
(5)
— SP4 SP3 SP2 SP1 SP0 00-0 0000 47, 53
PCLATU
— — — Holding Register for PC<20:16> ---0 0000 47, 52
PCLATH Holding Register for PC<15:8> 0000 0000 47, 52
PCL PC Low Byte (PC<7:0>) 0000 0000 47, 52
TBLPTRU
— — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 47, 74
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 47, 74
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 47, 74
TABLAT Program Memory Table Latch 0000 0000 47, 74
PRODH Product Register High Byte xxxx xxxx 47, 85
PRODL Product Register Low Byte xxxx xxxx 47, 85
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 47, 95
INTCON2 RBPU
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 1111 1111 47, 96
INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 1100 0000 47, 97
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 47, 66
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 47, 66
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 47, 66
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 47, 66
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A 47, 66
FSR0H
— — — — Indirect Data Memory Address Pointer 0 High Byte ---- 0000 47, 66
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 47, 66
WREG Working Register xxxx xxxx 47, 54
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 47, 66
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 47, 66
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 47, 66
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 47, 66
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A 47, 66
FSR1H
— — — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000 47, 66
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 47, 66
BSR
— — — — Bank Select Register ---- 0000 47, 57
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 48, 66
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 48, 66
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 48, 66
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 48, 66
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A 48, 66
FSR2H
— — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 48, 66
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 48, 66
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads
as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”.
2: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See
Section 3.6.4 “PLL in INTOSC Modes”.
3: The RA5 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RA5 reads as
‘0’. This bit is read-only.
4: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
5: Bit 7 and bit 6 are cleared by user software or by a POR.
6: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L.
7: This bit has no effect if the Configuration bit, WDTEN, is enabled.