Datasheet

PIC18F1230/1330
DS39758D-page 4  2009 Microchip Technology Inc.
Pin Diagrams
18-Pin PDIP, SOIC
2
3
4
5
6
1
8
7
9
RA0/AN0/INT0/KBI0/CMP0
RA1/AN1/INT1/KBI1
RA4/T0CKI/AN2/V
REF+
V
SS/AVSS
RA2/TX/CK
RA3/RX/DT
RB0/PWM0
RB1/PWM1
PIC18F1X30
17
16
15
14
13
18
11
12
10
RB3/INT3/KBI3/CMP1/T1OSI
(1)
RA7/OSC1/CLKI/T1OSI
(1)
/FLTA
(2)
RA6/OSC2/CLKO/T1OSO
(1)
/T1CKI
(1)
/AN3
V
DD/AVDD
RB7/PWM5/PGD
RB6/PWM4/PGC
RB5/PWM3
RB4/PWM2
20-Pin SSOP
Note 1: Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of
CONFIG3H.
2: Placement of FLTA
depends on the value of Configuration bit, FLTAMX, of CONFIG3H.
MCLR/VPP/RA5/FLTA
(2)
2
3
4
5
6
1
8
7
9
RA0/AN0/INT0/KBI0/CMP0
RA1/AN1/INT1/KBI1
RA4/T0CKI/AN2/V
REF+
V
SS
RA2/TX/CK
RA3/RX/DT
RB0/PWM0
RB1/PWM1
PIC18F1X30
19
18
17
16
15
20
13
14
12
RB3/INT3/KBI3/CMP1/T1OSI
(1)
RA7/OSC1/CLKI/T1OSI
(1)
/FLTA
(2)
VDD
RB7/PWM5/PGD
RB6/PWM4/PGC
RB5/PWM3
RB4/PWM2
MCLR/VPP/RA5/FLTA
(2)
10
11
AVSS
AVDD
RB2/INT2/KBI2/CMP2/T1OSO
(1)
/T1CKI
(1)
RA6/OSC2/CLKO/T1OSO
(1)
/T1CKI
(1)
/AN3
RB2/INT2/KBI2/CMP2/T1OSO
(1)
/T1CKI
(1)