Datasheet

PIC18F1230/1330
 2009 Microchip Technology Inc. DS39758D-page 289
FIGURE 23-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
FIGURE 23-9: BROWN-OUT RESET TIMING
TABLE 23-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol Characteristic Min Typ Max Units Conditions
30 TmcL MCLR
Pulse Width (low) 2 — — s
31 T
WDT Watchdog Timer Time-out Period
(no postscaler)
3.4 4.0 4.6 ms
32 T
OST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 period
33 T
PWRT Power-up Timer Period 55.6 65.5 75 ms
34 T
IOZ I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
—2—s
35 T
BOR Brown-out Reset Pulse Width 200 — — sVDD  BVDD (see D005)
36 T
IRVST Time for Internal Reference
Voltage to become Stable
—2050 s
37 T
LVD Low-Voltage Detect Pulse Width 200 — — sVDD  VLVD
38 TCSD CPU Start-up Time — 10 — s
39 TIOBST Time for INTOSC to Stabilize — 1 — s
VDD
MCLR
Internal
POR
PWRT
Time-out
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O pins
34
Note: Refer to Figure 23-5 for load conditions.
VDD
BVDD
35
VIRVST
Enable Internal
Internal Reference
36
Reference Voltage
Voltage Stable