Datasheet

PIC18F1230/1330
DS39758D-page 158  2009 Microchip Technology Inc.
FIGURE 15-3: EUSART TRANSMIT BLOCK DIAGRAM
FIGURE 15-4: ASYNCHRONOUS TRANSMISSION
FIGURE 15-5: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
TXIF
TXIE
Interrupt
TXEN
Baud Rate CLK
SPBRG
Baud Rate Generator
TX9D
MSb
LSb
Data Bus
TXREG Register
TSR Register
(8)
0
TX9
TRMT
SPEN
TX pin
Pin Buffer
and Control
8

SPBRGH
BRG16
Word 1
Word 1
Transmit Shift Reg
Start bit bit 0 bit 1 bit 7/8
Write to TXREG
BRG Output
(Shift Clock)
TX (pin)
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
1 TCY
Stop bit
Word 1
Transmit Shift Reg.
Write to TXREG
BRG Output
(Shift Clock)
TX (pin)
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Word 2
Word 1
Word 2
Stop bit
Start bit
Transmit Shift Reg.
Word 1
Word 2
bit 0 bit 1
bit 7/8
bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
Start bit