PIC18F1230/1330 Data Sheet High-Performance Microcontrollers with 10-bit A/D and nanoWatt Technology 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC18F1230/1330 18/20/28-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D Power-Managed Modes: Peripheral Highlights: • • • • • • • • • • • • • • Run: CPU on, peripherals on Idle: CPU off, peripherals on Sleep: CPU off, peripherals off Ultra Low 50 nA Input Leakage Run mode currents down to 15 A, typical Idle mode currents down to 3.7 A, typical Sleep mode current down to 100 nA, typical Timer1 Oscillator: 1.8 A, typical; 32 kHz; 2V Watchdog Timer (WDT): 1.
PIC18F1230/1330 Pin Diagrams 18-Pin PDIP, SOIC 1 18 RB3/INT3/KBI3/CMP1/T1OSI(1) RA1/AN1/INT1/KBI1 2 17 RB2/INT2/KBI2/CMP2/T1OSO(1)/T1CKI(1) RA4/T0CKI/AN2/VREF+ 3 16 RA7/OSC1/CLKI/T1OSI(1)/FLTA(2) MCLR/VPP/RA5/FLTA(2) 4 15 RA6/OSC2/CLKO/T1OSO(1)/T1CKI(1)/AN3 VSS/AVSS 5 14 VDD/AVDD RA2/TX/CK 6 13 RB7/PWM5/PGD RA3/RX/DT 7 12 RB6/PWM4/PGC RB0/PWM0 8 11 RB5/PWM3 RB1/PWM1 9 10 RB4/PWM2 PIC18F1X30 RA0/AN0/INT0/KBI0/CMP0 20-Pin SSOP 1 20 RB3/INT3/KBI3/CMP1/T1OSI(1) RA1/AN1/
PIC18F1230/1330 Pin Diagrams (Continued) RA4/T0CKI/AN2/VREF+ RA1/AN1/INT1/KBI1 RA0/AN0/INT0/KBI0/CMP0 NC RB3/INT3/KBI3/CMP1/T1OSI(1) RB2/INT2/KBI2/CMP2/T1OSO(1)/T1CKI(1) NC 28-Pin QFN(3) 28 27 26 25 24 23 22 1 2 3 4 5 6 7 PIC18F1X30 8 9 10 11 12 13 14 21 20 19 18 17 16 15 RA7/OSC1/CLKI/T1OSI(1)/FLTA(2) RA6/OSC2/CLKO/T1OSO(1)/T1CKI(1)/AN3 VDD NC AVDD RB7/PWM5/PGD RB6/PWM4/PGC RA3/RX/DT RB0/PWM0 RB1/PWM1 NC RB4/PWM2 RB5/PWM3 NC MCLR/VPP/RA5/FLTA(2) NC VSS NC AVSS NC RA2/TX/CK Note 1: 2: 3: Placemen
PIC18F1230/1330 Table of Contents 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0 Device Overview .......................................................................................................................................................................... 9 Guidelines for Getting Started with PIC18F Microcontrollers ..................................................................................................... 17 Oscillator Configurations ......
PIC18F1230/1330 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.
PIC18F1230/1330 NOTES: DS39758D-page 8 2009 Microchip Technology Inc.
PIC18F1230/1330 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F1230 • PIC18F1330 • PIC18LF1230 • PIC18LF1330 This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price – with the addition of highendurance Enhanced Flash program memory.
PIC18F1230/1330 1.2 Other Special Features • Memory Endurance: The Enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. • Self-Programmability: These devices can write to their own program memory spaces under internal software control.
PIC18F1230/1330 TABLE 1-1: DEVICE FEATURES Features PIC18F1230 PIC18F1330 DC – 40 MHz DC – 40 MHz Program Memory (Bytes) 4096 8192 Program Memory (Instructions) 2048 4096 Data Memory (Bytes) 256 256 Data EEPROM Memory (Bytes) 128 128 Interrupt Sources 17 17 Ports A, B Ports A, B 2 2 Operating Frequency I/O Ports Timers Power Control PWM Module 6 Channels 6 Channels Serial Communications Enhanced USART Enhanced USART 10-Bit Analog-to-Digital Module 4 Input Channels 4 Input C
PIC18F1230/1330 FIGURE 1-1: PIC18F1230/1330 (18-PIN) BLOCK DIAGRAM Data Bus<8> 21 Table Pointer <2> 8 8 8 RA0/AN0/INT0/KBI0/CMP0 Data RAM inc/dec logic 21 PORTA Data Latch 8 RA1/AN1/INT1/KBI1 21 Address Latch 20 Address Latch Program Memory (4 Kbytes) PIC18F1230 (8 Kbytes) PIC18F1330 PCLATU PCLATH PCU PCH PCL Program Counter 4 BSR 31 Level Stack Data Latch 16 Decode Table Latch 8 RA2/TX/CK 12 Address<12> 12 RA3/RX/DT 4 RA4/T0CKI/AN2/VREF+ FSR0 Bank0, F FSR1 FSR2 12 MCLR/VPP/RA5(
PIC18F1230/1330 TABLE 1-2: PIC18F1230/1330 PINOUT I/O DESCRIPTIONS Pin Number Pin Name MCLR/VPP/RA5/FLTA PDIP, SSOP SOIC 4 4 QFN Pin Type 1 MCLR I VPP RA5 FLTA(1) I I I RA7/OSC1/CLKI/ T1OSI/FLTA RA7 OSC1 16 18 21 I/O I I I I CLKI T1OSI(2) FLTA(1) RA6/OSC2/CLKO/ T1OSO/T1CKI/AN3 RA6 OSC2 15 CLKO T1OSO(2) TICKI(2) AN3 17 20 I/O O O O I I Buffer Type Description Master Clear (input), programming voltage (input) or Fault detect input. ST Master Clear (Reset) input.
PIC18F1230/1330 TABLE 1-2: PIC18F1230/1330 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP, SSOP SOIC QFN Pin Type Buffer Type Description PORTA is a bidirectional I/O port. RA0/AN0/INT0/KBI0/ CMP0 RA0 AN0 INT0 KBI0 CMP0 1 RA1/AN1/INT1/KBI1 RA1 AN1 INT1 KBI1 2 RA2/TX/CK RA2 TX CK 6 RA3/RX/DT RA3 RX DT 7 RA4/T0CKI/AN2/VREF+ RA4 T0CKI AN2 VREF+ 3 1 2 7 8 3 26 I/O I I I I TTL Analog ST TTL Analog Digital I/O. Analog input 0. External interrupt 0. Interrupt-on-change pin.
PIC18F1230/1330 TABLE 1-2: PIC18F1230/1330 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP, SSOP SOIC QFN Pin Type Buffer Type Description PORTB is a bidirectional I/O port.
PIC18F1230/1330 TABLE 1-2: PIC18F1230/1330 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP, SSOP SOIC QFN Pin Type Buffer Type Description VSS 5 5 3 P — Ground reference for logic and I/O pins. VDD 14 16 19 P — Positive supply for logic and I/O pins. AVSS 5 6 5 P — Ground reference for A/D Converter module. AVDD 14 15 17 P — Positive supply for A/D Converter module. NC — — 2, 4, 6, 11, 14, 18, 22, 25 — — No Connect.
PIC18F1230/1330 2.
PIC18F1230/1330 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.
PIC18F1230/1330 2.3 Master Clear (MCLR) Pin The MCLR pin provides two specific device functions: Device Reset, and Device Programming and Debugging. If programming and debugging are not required in the end application, a direct connection to VDD may be all that is required. The addition of other components, to help increase the application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1.
PIC18F1230/1330 2.5 External Oscillator Pins FIGURE 2-3: Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 3.0 “Oscillator Configurations” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins.
PIC18F1230/1330 3.0 OSCILLATOR CONFIGURATIONS 3.1 Oscillator Types PIC18F1230/1330 devices can be operated in ten different oscillator modes. The user can program the Configuration bits, FOSC3:FOSC0, in Configuration Register 1H to select one of these ten modes: 1. 2. 3. 4. LP XT HS HSPLL Low-Power Crystal Crystal/Resonator High-Speed Crystal/Resonator High-Speed Crystal/Resonator with PLL enabled 5. RC External Resistor/Capacitor with FOSC/4 output on RA6 6.
PIC18F1230/1330 TABLE 3-2: Osc Type CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq Typical Capacitor Values Tested: C1 C2 LP 32 kHz 30 pF 30 pF XT 1 MHz 4 MHz 15 pF 15 pF 15 pF 15 pF 4 MHz 10 MHz 20 MHz 25 MHz 15 pF 15 pF 15 pF 15 pF 15 pF 15 pF 15 pF 15 pF HS An external clock source may also be connected to the OSC1 pin in the HS mode, as shown in Figure 3-2. FIGURE 3-2: EXTERNAL CLOCK INPUT OPERATION (HS OSCILLATOR CONFIGURATION) OSC1 Clock from Ext.
PIC18F1230/1330 3.4 RC Oscillator 3.5 For timing insensitive applications, the “RC” and “RCIO” device options offer additional cost savings.
PIC18F1230/1330 3.6 Internal Oscillator Block The PIC18F1230/1330 devices include an internal oscillator block which generates two different clock signals; either can be used as the microcontroller’s clock source. This may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC) is an 8 MHz clock source, which can be used to directly drive the device clock. It also drives a postscaler, which can provide a range of clock frequencies from 31 kHz to 4 MHz.
PIC18F1230/1330 REGISTER 3-1: OSCTUNE: OSCILLATOR TUNING REGISTER R/W-0 R/W-0(1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN(1) — TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.
PIC18F1230/1330 Clock Sources and Oscillator Switching Like previous PIC18 devices, the PIC18F1230/1330 family includes a feature that allows the device clock source to be switched from the main oscillator to an alternate low-frequency clock source. PIC18F1230/1330 devices offer two alternate clock sources. When an alternate clock source is enabled, the various power-managed operating modes are available.
PIC18F1230/1330 3.7.1 OSCILLATOR CONTROL REGISTER The OSCCON register (Register 3-2) controls several aspects of the device clock’s operation, both in full power operation and in power-managed modes. The System Clock Select bits, SCS1:SCS0, select the clock source. The available clock sources are the primary clock (defined by the FOSC3:FOSC0 Configuration bits), the secondary clock (Timer1 oscillator) and the internal oscillator block.
PIC18F1230/1330 REGISTER 3-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 R/W-1 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF2:IRCF0: Internal Oscil
PIC18F1230/1330 3.8 Effects of Power-Managed Modes on the Various Clock Sources When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin, if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the device clock.
PIC18F1230/1330 NOTES: DS39758D-page 30 2009 Microchip Technology Inc.
PIC18F1230/1330 4.0 4.1.1 POWER-MANAGED MODES The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: PIC18F1230/1330 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices).
PIC18F1230/1330 4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: • OSTS (OSCCON<3>) • IOFS (OSCCON<2>) • T1RUN (T1CON<6>) In general, only one of these bits will be set while in a given power-managed mode.
PIC18F1230/1330 FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 1 T1OSI 2 3 n-1 Q3 Q4 Q1 Q2 Q3 n Clock Transition(1) OSC1 CPU Clock Peripheral Clock Program Counter Note 1: PC PC + 2 PC + 4 Clock transition typically occurs within 2-4 TOSC.
PIC18F1230/1330 If the IRCF bits and the INTSRC bit are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the device clocks. On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 4-4).
PIC18F1230/1330 4.3 Sleep Mode 4.4 The power-managed Sleep mode in the PIC18F1230/ 1330 devices is identical to the legacy Sleep mode offered in all other PIC devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 4-5). All clock source status bits are cleared. Entering the Sleep mode from any other mode does not require a clock switch.
PIC18F1230/1330 4.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “warm-up” or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction.
PIC18F1230/1330 4.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then set the SCS1 bit and execute SLEEP.
PIC18F1230/1330 4.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. There are two cases: • PRI_IDLE mode, where the primary clock source is not stopped; and • the primary clock source is not any of the LP, XT, HS or HSPLL modes.
PIC18F1230/1330 5.0 RESET The PIC18F1230/1330 devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during power-managed modes Watchdog Timer (WDT) Reset (during execution) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset This section discusses Resets generated by MCLR, POR and BOR and covers the operation of the various start-up timers.
PIC18F1230/1330 REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1(1) U-0 R/W-1 R-1 R-1 R/W-0(2) R/W-0 IPEN SBOREN — RI TO PD POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Softwa
PIC18F1230/1330 5.2 Master Clear (MCLR) The MCLR pin provides a method for triggering an external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. FIGURE 5-2: In PIC18F1230/1330 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 10.1 “PORTA, TRISA and LATA Registers” for more information. 5.
PIC18F1230/1330 5.4 Brown-out Reset (BOR) PIC18F1230/1330 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV1:BORV0 and BOREN1:BOREN0 Configuration bits. There are a total of four BOR configurations which are summarized in Table 5-1. The BOR threshold is set by the BORV1:BORV0 bits.
PIC18F1230/1330 5.5 5.5.3 Device Reset Timers With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly different from other oscillator modes. A separate timer is used to provide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the oscillator start-up time-out.
PIC18F1230/1330 FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 5-5: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS39758D-page 44 2009 Micr
PIC18F1230/1330 FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) FIGURE 5-7: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT OST TIME-OUT TOST TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL 2 ms max. First three stages of the PWRT timer. 2009 Microchip Technology Inc.
PIC18F1230/1330 5.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Table 5-4 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups.
PIC18F1230/1330 TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt TOSU 1230 1330 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 1230 1330 0000 0000 0000 0000 uuuu uuuu(3) TOSL 1230 1330 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 1230 1330 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU 1230 1330 ---0 0000 ---0 0000 ---u uuuu PCLATH 1230 1330
PIC18F1230/1330 TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt INDF2 1230 1330 N/A N/A N/A POSTINC2 1230 1330 N/A N/A N/A POSTDEC2 1230 1330 N/A N/A N/A PREINC2 1230 1330 N/A N/A N/A PLUSW2 1230 1330 N/A N/A N/A FSR2H 1230 1330 ---- 0000 ---- 0000 ---- uuuu FSR2L 1230 1330 xxxx xxxx uuuu uuuu uuuu uu
PIC18F1230/1330 TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt EEADR 1230 1330 0000 0000 0000 0000 uuuu uuuu EEDATA 1230 1330 0000 0000 0000 0000 uuuu uuuu EECON2 1230 1330 0000 0000 0000 0000 0000 0000 EECON1 1230 1330 xx-0 x000 uu-0 u000 uu-0 u000 IPR3 1230 1330 ---1 ---- ---1 ---- ---u ---- PIR3 1230 1330
PIC18F1230/1330 TABLE 5-4: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt SEVTCMPH 1230 1330 ---- 0000 ---- 0000 ---- uuuu PWMCON0 1230 1330 -100 -000(6) -100 -000(6) -uuu -uuu(6) -000 -000(6) -000 -000(6) -uuu -uuu(6) 1330 0000 0-00 0000 0-00 uuuu u-uu PWMCON1 1230 DTCON 1230 1330 0000 0000 0000 0000 uuuu uuuu OVDCOND 1230
PIC18F1230/1330 MEMORY ORGANIZATION 6.1 There are three types of memory in PIC18 Enhanced microcontroller devices: • Program Memory • Data RAM • Data EEPROM As Harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. The data EEPROM, for practical purposes, can be regarded as a peripheral device, since it is addressed and accessed through a set of control registers.
PIC18F1230/1330 6.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU.
PIC18F1230/1330 6.1.2.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs. The STKPTR register (Register 6-1) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits.
PIC18F1230/1330 6.1.2.4 Stack Full and Underflow Resets Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit but not cause a device Reset.
PIC18F1230/1330 6.2 6.2.2 PIC18 Instruction Cycle 6.2.1 CLOCKING SCHEME The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the program counter is incremented on every Q1; the instruction is fetched from the program memory and latched into the Instruction Register (IR) during Q4. The instruction is decoded and executed during the following Q1 through Q4.
PIC18F1230/1330 6.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSb will always read ‘0’ (see Section 6.1.1 “Program Counter”).
PIC18F1230/1330 6.3 Note: Data Memory Organization The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 6.5 “Data Memory and the Extended Instruction Set” for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory.
PIC18F1230/1330 FIGURE 6-5: DATA MEMORY MAP FOR PIC18F1230/1330 DEVICES BSR<3:0> = 0000 When a = 0: Data Memory Map 00h Access RAM FFh GPR Bank 0 000h 07Fh 080h 0FFh The BSR is ignored and the Access Bank is used. The first 128 bytes are general purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When a = 1: The BSR specifies the Bank used by the instruction.
PIC18F1230/1330 FIGURE 6-6: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) 7 0 0 0 0 0 0 0 0 0 000h Bank 0 Bank Select(2) 100h From Opcode(2) 7 Data Memory 00h 1 1 1 1 1 1 0 1 1 FFh 00h Bank 1 through Bank 13 E00h Bank 14 F00h FFFh Note 1: 2: 6.3.2 Bank 15 FFh 00h FFh 00h FFh The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank.
PIC18F1230/1330 6.3.4 SPECIAL FUNCTION REGISTERS The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, Resets and interrupts) and those related to the peripheral functions. The Reset and Interrupt registers are described in their respective chapters, while the ALU’s STATUS register is described later in this section. Registers related to the operation of a peripheral feature are described in the chapter for that peripheral.
PIC18F1230/1330 TABLE 6-2: File Name REGISTER FILE SUMMARY (PIC18F1230/1330) Bit 7 Bit 6 Bit 5 — — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Details on Page: ---0 0000 47, 52 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 47, 52 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 47, 52 00-0 0000 47, 53 TOSU STKPTR PCLATU STKFUL(5) STKUNF(5) — — — — Top-of-Stack Upper Byte (TOS<20:16>) Value on POR, BOR SP4 SP3 SP2 SP1 SP0 ---0 0000 47, 52 PCLATH Holding Register for PC<15:8>
PIC18F1230/1330 TABLE 6-2: File Name STATUS REGISTER FILE SUMMARY (PIC18F1230/1330) (CONTINUED) Details on Page: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR — — — N OV Z DC C ---x xxxx 48, 64 0000 0000 48, 109 TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte xxxx xxxx 48, 109 TMR0ON T016BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 48, 107 OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 48, 28 LVDCON — — IR
PIC18F1230/1330 TABLE 6-2: File Name PTMRL REGISTER FILE SUMMARY (PIC18F1230/1330) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWM Time Base Register (lower 8 bits) PTMRH — PTPERL PTPERH TRISB — — — PWM Time Base Register (upper 4 bits) — PWM Time Base Period Register (upper 4 bits) PWM Time Base Period Register (lower 8 bits) — — — PORTB Data Direction Control Register TRISA7(4) TRISA PDC0L TRISA6(4) PORTA Data Direction Control Register PWM Duty Cycle #0L Register
PIC18F1230/1330 6.3.5 STATUS REGISTER The STATUS register, shown in Register 6-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the STATUS register is updated according to the instruction performed.
PIC18F1230/1330 6.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 6.5 “Data Memory and the Extended Instruction Set” for more information. The data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed.
PIC18F1230/1330 6.4.3.1 FSR Registers and the INDF Operand 6.4.3.2 At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations.
PIC18F1230/1330 The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 6.4.3.3 Operations by FSRs on FSRs Indirect Addressing operations that target other FSRs or virtual registers represent special cases.
PIC18F1230/1330 FIGURE 6-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When ‘a’ = 0 and f 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and 0FFh. This is the same as locations 060h to 07Fh (Bank 0) and F80h to FFFh (Bank 15) of data memory.
PIC18F1230/1330 6.5.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET ADDRESSING MODE The use of Indexed Literal Offset Addressing mode effectively changes how the first 96 locations of Access RAM (00h to 5Fh) are mapped. Rather than containing just the contents of the bottom half of Bank 0, this mode maps the contents from Bank 0 and a user-defined “window” that can be located anywhere in the data memory space.
PIC18F1230/1330 NOTES: DS39758D-page 70 2009 Microchip Technology Inc.
PIC18F1230/1330 7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 8 bytes at a time.
PIC18F1230/1330 FIGURE 7-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 8 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 7.5 “Writing to Flash Program Memory”. 7.
PIC18F1230/1330 REGISTER 7-1: R/W-x EECON1: EEPROM CONTROL REGISTER 1 R/W-x EEPGD CFGS U-0 — R/W-0 FREE R/W-x (1) WRERR R/W-0 R/S-0 R/S-0 WREN WR RD bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data E
PIC18F1230/1330 7.2.2 TABLAT – TABLE LATCH REGISTER 7.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 7.2.3 TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT.
PIC18F1230/1330 7.3 Reading the Flash Program Memory The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 7-4 shows the interface between the internal program memory and the TABLAT. TBLPTR points to a byte address in program space.
PIC18F1230/1330 7.4 7.4.1 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. The sequence of events for erasing a block of internal program memory location is: 1. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased.
PIC18F1230/1330 The minimum programming block is 4 words or 8 bytes. Word or byte programming is not supported. The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 8 holding registers used by the table writes for programming.
PIC18F1230/1330 EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'88 COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; number of bytes in erase block TBLRD*+ MOVF MOVWF DECFSZ BRA TABLAT, W POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; point to b
PIC18F1230/1330 EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BSF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF Required Sequence 7.5.
PIC18F1230/1330 NOTES: DS39758D-page 80 2009 Microchip Technology Inc.
PIC18F1230/1330 8.0 DATA EEPROM MEMORY 8.2 EECON1 and EECON2 Registers The data EEPROM is readable and writable during normal operation over the entire VDD range. The data memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFR). Access to the data EEPROM is controlled by two registers: EECON1 and EECON2.
PIC18F1230/1330 REGISTER 8-1: R/W-x EECON1: EEPROM CONTROL REGISTER 1 R/W-x EEPGD CFGS U-0 — R/W-0 FREE R/W-x (1) WRERR R/W-0 R/S-0 R/S-0 WREN WR RD bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data E
PIC18F1230/1330 8.3 After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruction. Both WR and WREN cannot be set with the same instruction. Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit RD (EECON1<0>).
PIC18F1230/1330 8.7 Operation During Code-Protect 8.8 Data EEPROM memory has its own code-protect bits in Configuration Words. External read and write operations are disabled if either of these mechanisms are enabled. Using the Data EEPROM The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often).
PIC18F1230/1330 9.0 8 x 8 HARDWARE MULTIPLIER 9.1 Introduction EXAMPLE 9-1: MOVF MULWF All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the Product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS register.
PIC18F1230/1330 Example 9-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 9-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0).
PIC18F1230/1330 10.0 I/O PORTS Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation.
PIC18F1230/1330 TABLE 10-1: PORTA I/O SUMMARY Pin RA0/AN0/INT0/ KBI0/CMP0 RA1/AN1/INT1/ KBI1 RA2/TX/CK RA3/RX/DT RA4/T0CKI/AN2/ VREF+ MCLR/VPP/RA5/ FLTA Function TRIS Setting I/O I/O Type RA0 0 O DIG 1 I TTL PORTA<0> data input; disabled when analog input enabled. AN0 1 I ANA Analog input 0. INT0 1 I ST KBI0 1 I TTL Interrupt-on-change pin. CMP0 1 I ANA Comparator 0 input. RA1 0 O DIG LATA<1> data output; not affected by analog input.
PIC18F1230/1330 TABLE 10-2: Name PORTA SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 RA7(1) RA6(1) (1) LATA6(1) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RA5 RA4 RA3 RA2 RA1 RA0 PORTA Output Latch Register (Read and Write to Data Latch) LATA LATA7 TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Control Register INTCON GIE/GIEH PEIE/GIEL INTCON2 RBPU INTEDG0 TMR0IE INT0IE RBIE INTEDG1 INTEDG2 INTEDG3 Reset Values on Page: 50 49 49 TMR0IF INT0IF RBIF 47 TMR0IP INT3IP
PIC18F1230/1330 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Output Latch register (LATB) is also memory mapped.
PIC18F1230/1330 TABLE 10-3: Pin RB0/PWM0 RB1PWM1 RB2/INT2/KBI2/ CMP2/T1OSO/ T1CKI RB3/INT3/KBI3/ CMP1/T1OSI RB4/PWM2 RB5/PWM3 RB6/PWM4/PGC RB7/PWM5/PGD Legend: Note 1: 2: PORTB I/O SUMMARY Function TRIS Setting I/O I/O Type RB0 0 O DIG LATB<0> data output; not affected by analog input. 1 I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) Description PWM0 0 O DIG PWM module output PWM0.
PIC18F1230/1330 TABLE 10-4: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 50 PORTB LATB PORTB Output Latch Register (Read and Write to Data Latch) 49 TRISB PORTB Data Direction Control Register 49 INTCON INTCON2 GIE/GIEH PEIE/GIEL RBPU TMR0IF INT0IF RBIF 47 INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP TMR0IE INT0IE RBIE INT3IP RBIP 47 INTCON3 INT2IP INT1IP INT3IE INT2IE
PIC18F1230/1330 11.0 INTERRUPTS The PIC18F1230/1330 devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress. There are thirteen registers which are used to control interrupt operation.
PIC18F1230/1330 FIGURE 11-1: PIC18 INTERRUPT LOGIC TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP Wake-up if in Idle or Sleep modes INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit GIE/GIEH ADIF ADIE ADIP From Power Control PWM Interrupt Logic Interrupt to CPU Vector to Location 0008h IPEN IPEN PTIF PTIE PTIP PEIE/GIEL IPEN Additional Peripheral Interrupts High-Priority Interrupt Generation Low-Priority In
PIC18F1230/1330 11.1 INTCON Registers Note: The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits. REGISTER 11-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
PIC18F1230/1330 REGISTER 11-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Inter
PIC18F1230/1330 REGISTER 11-3: INTCON3: INTERRUPT CONTROL REGISTER 3 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low pr
PIC18F1230/1330 11.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2 and PIR3). Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>).
PIC18F1230/1330 REGISTER 11-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 U-0 U-0 OSCFIF — — EEIF — LVDIF — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = Device clock operating
PIC18F1230/1330 11.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2 and PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
PIC18F1230/1330 REGISTER 11-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 U-0 U-0 OSCFIE — — EEIE — LVDIE — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6-5 Unimplemented: Read as ‘0’ bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable
PIC18F1230/1330 11.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2 and IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
PIC18F1230/1330 REGISTER 11-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 U-0 U-0 R/W-1 U-0 R/W-1 U-0 U-0 OSCFIP — — EEIP — LVDIP — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6-5 Unimplemented: Read as ‘0’ bit 4 EEIP: Data EEPROM/Flash Write Operation Inte
PIC18F1230/1330 11.5 The operation of the SBOREN bit and the Reset flag bits is discussed in more detail in Section 5.1 “RCON Register”. RCON Register The RCON register contains flag bits which are used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the IPEN bit which enables interrupt priorities.
PIC18F1230/1330 11.6 INTx Pin Interrupts 11.7 External interrupts on the RA0/INT0, RA1/INT1, RB2/ INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the pin, the corresponding flag bit, INTxIF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxIE.
PIC18F1230/1330 NOTES: DS39758D-page 106 2009 Microchip Technology Inc.
PIC18F1230/1330 12.0 Figure 12-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 12-2 shows a simplified block diagram of the Timer0 module in 16-bit mode.
PIC18F1230/1330 FIGURE 12-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE Data Bus FOSC/4 0 8 T0CKI pin 1 Sync with Internal Clocks 1 Programmable Prescaler T0SE TMR0 0 (2 TCY Delay) 3 PSA Set Interrupt Flag bit TMR0IF on Overflow T0PS2, T0PS1, T0PS0 T0CS Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
PIC18F1230/1330 12.1 12.2.1 Timer0 Operation Timer0 can operate as a timer or as a counter. The prescaler assignment is fully under software control (i.e., it can be changed “on-the-fly” during program execution). Timer mode is selected by clearing the T0CS bit. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles.
PIC18F1230/1330 NOTES: DS39758D-page 110 2009 Microchip Technology Inc.
PIC18F1230/1330 13.0 TIMER1 MODULE The Timer1 timer/counter module has the following features: • 16-bit timer/counter (two 8-bit registers; TMR1H and TMR1L) • Readable and writable (both registers) • Internal or external clock select • Interrupt on overflow from FFFFh to 0000h • Status of system clock operation Figure 13-1 is a simplified block diagram of the Timer1 module. REGISTER 13-1: Register 13-1 details the Timer1 Control register.
PIC18F1230/1330 13.1 When TMR1CS = 0, Timer1 increments every instruction cycle. When TMR1CS = 1, Timer1 increments on every rising edge of the external clock input or the Timer1 oscillator, if enabled. Timer1 Operation Timer1 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter When the Timer1 oscillator is enabled (T1OSCEN is set), the T1OSI and T1OSO/T1CKI pins become inputs.
PIC18F1230/1330 13.2 13.2.1 Timer1 Oscillator A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO/TICKI (amplifier output). The placement of these pins depends on the value of Configuration bit, T1OSCMX (see Section 20.1 “Configuration Bits”). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator rated for 32 kHz crystals. It will continue to run during all power-managed modes.
PIC18F1230/1330 13.4 Timer1 Interrupt The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing Timer1 interrupt enable bit, TMR1IE (PIE1<0>). 13.5 Timer1 16-Bit Read/Write Mode Timer1 can be configured for 16-bit reads and writes (see Figure 13-2).
PIC18F1230/1330 EXAMPLE 13-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN 0x80 TMR1H TMR1L b'00001111' T1CON secs mins .12 hours PIE1, TMR1IE BSF BCF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN MOVLW MOVWF RETURN TMR1H, 7 PIR1, TMR1IF secs, F .
PIC18F1230/1330 NOTES: DS39758D-page 116 2009 Microchip Technology Inc.
PIC18F1230/1330 14.0 POWER CONTROL PWM MODULE The Power Control PWM module simplifies the task of generating multiple, synchronized Pulse-Width Modulated (PWM) outputs for use in the control of motor controllers and power conversion applications.
PIC18F1230/1330 FIGURE 14-1: POWER CONTROL PWM MODULE BLOCK DIAGRAM Internal Data Bus 8 PWMCON0 PWM Enable and Mode 8 PWMCON1 8 DTCON Dead-Time Control 8 FLTCONFIG Fault Pin Control 8 OVDCON 8 PWM Manual Control PWM Generator #2(1) PDC2 Buffer PDC2 Comparator 8 PWM Generator 1 PTMR Channel 2 Dead-Time Generator and Override Logic(1) Channel 1 Dead-Time Generator and Override Logic Comparator PWM Generator 0 PTPER PWM5 PWM4 Output Driver Block Channel 0 Dead-Time Generator and Ov
PIC18F1230/1330 FIGURE 14-2: PWM MODULE BLOCK DIAGRAM, ONE OUTPUT PAIR, COMPLEMENTARY MODE VDD Dead-Band Generator Duty Cycle Comparator PWM1 HPOL PWM Duty Cycle Register PWM0 LPOL Fault Override Values Channel Override Values Fault Pin Assignment Logic Fault A pin Note: In the Complementary mode, the even channel cannot be forced active by a Fault or override event when the odd channel is active.
PIC18F1230/1330 14.1 Control Registers The operation of the PWM module is controlled by a total of 20 registers.
PIC18F1230/1330 FIGURE 14-4: PWM TIME BASE BLOCK DIAGRAM PTMR Register PTMR Clock Timer Reset Up/Down Comparator Zero Match Period Match Comparator PTMOD1 Timer Direction Control PTDIR Duty Cycle Load PTPER Period Load PTPER Buffer Update Disable (UDIS) FOSC/4 Prescaler 1:1, 1:4, 1:16, 1:64 Zero Match Zero Match Period Match PTMOD1 PTMOD0 Clock Control PTMR Clock PTEN Postscaler 1:1-1:16 Interrupt Control PTIF Period Match PTMOD1 PTMOD0 The PWM time base can be configured for four diffe
PIC18F1230/1330 REGISTER 14-1: PTCON0: PWM TIMER CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTOPS3 PTOPS2 PTOPS1 PTOPS0 PTCKPS1 PTCKPS0 PTMOD1 PTMOD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 PTOPS3:PTOPS0: PWM Time Base Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale . . .
PIC18F1230/1330 REGISTER 14-3: PWMCON0: PWM CONTROL REGISTER 0 U-0 R/W-1(1) R/W-1(1) R/W-1(1) U-0 R/W-0 R/W-0 R/W-0 — PWMEN2 PWMEN1 PWMEN0 — PMOD2 PMOD1 PMOD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 PWMEN2:PWMEN0: PWM Module Enable bits(1) 111 = All odd PWM I/O pins enabled for PWM output 110 = PWM1, PWM3 pins enabl
PIC18F1230/1330 REGISTER 14-4: PWMCON1: PWM CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0 SEVTDIR — UDIS OSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 SEVOPS3:SEVOPS0: PWM Special Event Trigger Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale . . .
PIC18F1230/1330 14.3.1 FREE-RUNNING MODE In the Free-Running mode, the PWM time base (PTMRL and PTMRH) will begin counting upwards until the value in the PWM Time Base Period register, PTPER (PTPERL and PTPERH), is matched. The PTMR registers will be reset on the following input clock edge and the time base will continue counting upwards as long as the PTEN bit remains set. 14.3.2 SINGLE-SHOT MODE In the Single-Shot mode, the PWM time base will begin counting upwards when the PTEN bit is set.
PIC18F1230/1330 FIGURE 14-5: PWM TIME BASE INTERRUPT TIMING, FREE-RUNNING MODE A: PRESCALER = 1:1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 FOSC/4 1 PTMR FFEh FFFh 000h 002h 001h PTMR_INT_REQ PTIF bit B: PRESCALER = 1:4 Q4 Qc Qc Qc Qc Qc Qc Qc Qc Qc Q4 Qc Qc Qc Qc Qc Qc Qc Qc Qc Qc Qc 1 PTMR FFEh FFFh 000h 001h 002h PTMR_INT_REQ PTIF bit Note 1: 14.4.
PIC18F1230/1330 FIGURE 14-6: PWM TIME BASE INTERRUPT TIMING, SINGLE-SHOT MODE A: PRESCALER = 1:1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 FOSC/4 2 PTMR FFEh FFFh 1 000h 1 000h 000h 1 PTMR_INT_REQ PTIF bit B: PRESCALER = 1:4 Qc Q4 Qc Qc Qc Qc Qc Qc Qc Qc Q4 Qc Qc Qc Qc Qc Qc Qc Qc Qc Qc Qc 2 PTMR FFEh 000h FFFh 1 1 000h 000h 1 PTMR_INT_REQ PTIF bit Note 1: 2: Interrupt flag bit, PTIF, is sampled here (every Q1).
PIC18F1230/1330 14.4.4 INTERRUPTS IN DOUBLE UPDATE MODE 2. This mode is available in Continuous Up/Down Count mode. In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR register is equal to zero and each time the PTMR matches the PTPER register. Figure 14-8 shows the interrupts in Continuous Up/Down Count mode with double updates.
PIC18F1230/1330 14.5 PWM Period The PWM period is defined by the PTPER register pair (PTPERL and PTPERH). The PWM period has 12-bit resolution by combining 4 LSBs of PTPERH and 8 bits of PTPERL. PTPER is a double-buffered register used to set the counting period for the PWM time base.
PIC18F1230/1330 FIGURE 14-9: PWM PERIOD BUFFER UPDATES IN FREE-RUNNING MODE Period Value Loaded from PTPER Buffer Register 7 New PTPER Value = 007 6 5 4 Old PTPER Value = 004 4 4 3 3 3 2 2 2 1 1 1 0 0 0 New Value Written to PTPER Buffer FIGURE 14-10: PWM PERIOD BUFFER UPDATES IN CONTINUOUS UP/DOWN COUNT MODES Period Value Loaded from PTPER Buffer Register 7 New PTPER Value = 007 6 5 4 Old PTPER Value = 004 3 2 1 0 4 3 3 2 2 1 1 0 6 5 4 3 2 1 0 New Value Written to PTPER Buffer
PIC18F1230/1330 14.6 PWM Duty Cycle PWM duty cycle is defined by the PDCx (PDCxL and PDCxH) registers. There are a total of three PWM Duty Cycle registers for four pairs of PWM channels. The Duty Cycle registers have 14-bit resolution by combining the six LSbs of PDCxH with the 8 bits of PDCxL. PDCx is a double-buffered register used to set the counting period for the PWM time base. 14.6.
PIC18F1230/1330 14.6.2 DUTY CYCLE REGISTER BUFFERS The three PWM Duty Cycle registers are doublebuffered to allow glitchless updates of the PWM outputs. For each duty cycle block, there is a Duty Cycle Buffer register that is accessible by the user and a second Duty Cycle register that holds the actual compare value used in the present PWM period.
PIC18F1230/1330 FIGURE 14-14: DUTY CYCLE UPDATE TIMES IN CONTINUOUS UP/DOWN COUNT MODE WITH DOUBLE UPDATES Duty Cycle Value Loaded from Buffer Register PWM Output PTMR Value New Values Written to Duty Cycle Buffer 14.6.4 CENTER-ALIGNED PWM Center-aligned PWM signals are produced by the module when the PWM time base is configured in a Continuous Up/Down Count mode (see Figure 14-15).
PIC18F1230/1330 PWM5 3-Phase Load PWM4 PWM3 Each upper/lower power switch pair is fed by a complementary PWM signal. Dead time may be optionally inserted during device switching, where both outputs are inactive for a short period (see Section 14.7 “Dead-Time Generators”). TYPICAL LOAD FOR COMPLEMENTARY PWM OUTPUTS +V PWM2 The Complementary mode of PWM operation is useful to drive one or more power switches in half-bridge configuration, as shown in Figure 14-16.
PIC18F1230/1330 14.7 14.7.1 Dead-Time Generators In power inverter applications, where the PWMs are used in Complementary mode to control the upper and lower switches of a half-bridge, a dead-time insertion is highly recommended. The dead-time insertion keeps both outputs in inactive state for a brief time. This avoids any overlap in the switching during the state change of the power devices due to TON and TOFF characteristics.
PIC18F1230/1330 REGISTER 14-5: DTCON: DEAD-TIME CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTPS1 DTPS0 DT5 DT4 DT3 DT2 DT1 DT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 DTPS1:DTPS0: Dead-Time Unit A Prescale Select bits 11 = Clock source for dead-time unit is FOSC/16 10 = Clock source for dead-time unit is FOSC/8 01 = Clock source for dead-time unit
PIC18F1230/1330 The actual dead time is calculated from the DTCON register as follows: Dead Time = Dead-Time Value/(FOSC/Prescaler) Table 14-3 shows example dead-time ranges as a function of the input clock prescaler selected and the device operating frequency. TABLE 14-3: FOSC MIPS (MHz) EXAMPLE DEAD-TIME RANGES Prescaler Dead-Time Dead-Time Selection Min Max 40 10 FOSC/2 50 ns 3.2 s 40 10 FOSC/4 100 ns 6.4 s 40 10 FOSC/8 200 ns 12.8 s 40 10 FOSC/16 400 ns 25.
PIC18F1230/1330 14.8.2 PWM CHANNEL OVERRIDE PWM output may be manually overridden for each PWM channel by using the appropriate bits in the OVDCOND and OVDCONS registers. The user may select the following signal output options for each PWM output pin operating in the Independent PWM mode: • I/O pin outputs PWM signal • I/O pin inactive • I/O pin active Refer to Section 14.10 “PWM Output Override” for details for all the override functions. FIGURE 14-19: CENTER CONNECTED LOAD +V PWM1 Load PWM0 14.
PIC18F1230/1330 FIGURE 14-20: OVERRIDE BITS IN COMPLEMENTARY MODE 1 POUT0 POUT1 4 5 PWM1 2 7 3 PWM0 6 Assume: POVD0 = 0; POVD1 = 0; PMOD0 = 0 1. Even override bits have no effect in Complementary mode. 2. Odd override bit is activated which causes the even PWM to deactivate. 3. Dead-time insertion. 4. Odd PWM activated after the dead time. 5. Odd override bit is deactivated which causes the odd PWM to deactivate. 6. Dead-time insertion. 7. Even PWM is activated after the dead time.
PIC18F1230/1330 14.10.3 OUTPUT OVERRIDE EXAMPLES Figure 14-21 shows an example of a waveform that might be generated using the PWM output override feature. The figure shows a six-step commutation sequence for a BLDC motor. The motor is driven through a 3-phase inverter as shown in Figure 14-16. When the appropriate rotor position is detected, the PWM outputs are switched to the next commutation state in the sequence. In this example, the PWM outputs are driven to specific logic states.
PIC18F1230/1330 FIGURE 14-21: 1 PWM OUTPUT OVERRIDE EXAMPLE #1 2 3 4 6 5 14.11 PWM Output and Polarity Control There are three device Configuration bits associated with the PWM module that provide PWM output pin control defined in the CONFIG3L register. They are: • HPOL • LPOL • PWMPIN PWM5 PWM4 PWM3 These three Configuration bits work in conjunction with the three PWM Enable bits (PWMEN2:PWMEN0) in the PWMCON0 register.
PIC18F1230/1330 FIGURE 14-23: PWM I/O PIN BLOCK DIAGRAM PWM Signal from Module 1 0 PWM Pin Enable Data Bus WR PORT D Q CK VDD Q P Data Latch D WR TRIS CK I/O pin Q N Q VSS TRIS Latch TTL or Schmitt Trigger RD TRIS Q D EN RD PORT Note: 14.11.3 I/O pin has protection diodes to VDD and VSS. PWM polarity selection logic not shown for clarity.
PIC18F1230/1330 14.12.2 FAULT INPUT MODE 14.12.3 The FLTAMOD bit in the FLTCONFIG register determines whether the PWM I/O pins are deactivated when they are overridden by a Fault input. FLTAS bit in the FLTCONFIG register gives the status of the Fault A input. The Fault input has two modes of operation: • Inactive Mode (FLTAMOD = 0) This is a catastrophic Fault Management mode. When the Fault occurs in this mode, the PWM outputs are deactivated.
PIC18F1230/1330 14.13 PWM Update Lockout For a complex PWM application, the user may need to write up to four Duty Cycle registers and the PWM Time Base Period Register, PTPER, at a given time. In some applications, it is important that all buffer registers be written before the new duty cycle and period values are loaded for use by the module. A PWM update lockout feature may optionally be enabled so the user may specify when new duty cycle buffer values are valid.
PIC18F1230/1330 TABLE 14-6: Name REGISTERS ASSOCIATED WITH THE POWER CONTROL PWM MODULE Bit 7 INTCON Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47 IPR3 — — — PTIP — — — — 49 PIE3 — — — PTIE — — — — 49 — — — — PIR3 PTCON0 PTCON1 PTMRL(1) — — — PTIF PTOPS3 PTOPS2 PTOPS1 PTOPS0 PTEN PTDIR — — PTCKPS1 PTCKPS 0 — — PTMOD1 PTMOD0 — — PWM Time Base Register (lower 8 bits) PTMRH
PIC18F1230/1330 NOTES: DS39758D-page 146 2009 Microchip Technology Inc.
PIC18F1230/1330 15.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of the two serial I/O modules. (Generically, the USART is also known as a Serial Communications Interface or SCI.) The EUSART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers.
PIC18F1230/1330 REGISTER 15-1: R/W-0 TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 CSRC TX9 R/W-0 TXEN (1) R/W-0 R/W-0 R/W-0 R-1 R/W-0 SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care.
PIC18F1230/1330 REGISTER 15-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX
PIC18F1230/1330 REGISTER 15-3: BAUDCON: BAUD RATE CONTROL REGISTER R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rol
PIC18F1230/1330 15.1 Baud Rate Generator (BRG) The BRG is a dedicated 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCON<3>) selects 16-bit mode. The SPBRGH:SPBRG register pair controls the period of a free-running timer. In Asynchronous mode, bits BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>) also control the baud rate. In Synchronous mode, BRGH is ignored.
PIC18F1230/1330 EXAMPLE 15-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1)) Solving for SPBRGH:SPBRG: X = ((FOSC/Desired Baud Rate)/64) – 1 = ((16000000/9600)/64) – 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate = (9615 – 9600)/9600 = 0.
PIC18F1230/1330 TABLE 15-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) % Error 0.3 1.2 — — — — 2.4 2.441 1.73 FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error — — — 1.221 — 1.73 255 2.404 0.16 SPBRG value FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error — 255 — 1.202 — 0.16 129 2.404 SPBRG value FOSC = 8.000 MHz (decimal) Actual Rate (K) % Error — 129 — 1.201 — -0.16 — 103 0.16 64 2.403 -0.
PIC18F1230/1330 TABLE 15-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error 0.00 0.02 8332 2082 0.300 1.200 0.02 -0.03 2.402 0.06 1040 2.399 9.615 0.16 259 9.615 19.231 0.16 129 Actual Rate (K) % Error 0.3 1.2 0.300 1.200 2.4 9.6 19.2 SPBRG value FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error 4165 1041 0.300 1.200 -0.03 520 0.16 129 19.231 0.
PIC18F1230/1330 15.1.3 AUTO-BAUD RATE DETECT The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source.
PIC18F1230/1330 FIGURE 15-1: BRG Value AUTOMATIC BAUD RATE CALCULATION XXXXh RX pin 0000h 001Ch Start Edge #1 bit 1 bit 0 Edge #2 bit 3 bit 2 Edge #3 bit 5 bit 4 Edge #4 bit 7 bit 6 Edge #5 Stop bit BRG Clock Auto-Cleared Set by User ABDEN bit RCIF bit (interrupt) Read RCREG SPBRG XXXXh 1Ch SPBRGH XXXXh 00h Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
PIC18F1230/1330 15.2 EUSART Asynchronous Mode The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTA<4>). In this mode, the EUSART uses standard Non-Return-to-Zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8 bits. An on-chip dedicated 8-bit/16-bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator. The EUSART transmits and receives the LSb first.
PIC18F1230/1330 FIGURE 15-3: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG Register TXIE 8 MSb LSb (8) Pin Buffer and Control 0 TSR Register TX pin Interrupt TXEN Baud Rate CLK TRMT BRG16 SPBRGH SPBRG TX9 TX9D Baud Rate Generator FIGURE 15-4: Write to TXREG BRG Output (Shift Clock) ASYNCHRONOUS TRANSMISSION Word 1 TX (pin) Start bit FIGURE 15-5: bit 0 bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg.
PIC18F1230/1330 TABLE 15-5: Name INTCON REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47 PIR1 — ADIF RCIF TXIF CMP2IF CMP1IF CMP0IF TMR1IF 49 PIE1 — ADIE RCIE TXIE CMP2IE CMP1IE CMP0IE TMR1IE 49 — ADIP RCIP TXIP CMP2IP CMP1IP CMP0IP TMR1IP 49 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 48 IPR1 RCSTA TXREG TXSTA GIE/GIEH PEIE/GIEL Bit 5 EUSART Transm
PIC18F1230/1330 15.2.2 EUSART ASYNCHRONOUS RECEIVER 15.2.3 The receiver block diagram is shown in Figure 15-6. The data is received on the RX pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems.
PIC18F1230/1330 FIGURE 15-7: ASYNCHRONOUS RECEPTION Start bit RX (pin) bit 0 bit 7/8 Stop bit bit 1 Rcv Shift Reg Rcv Buffer Reg Start bit bit 0 Stop bit Start bit bit 7/8 Stop bit Word 2 RCREG Word 1 RCREG Read Rcv Buffer Reg RCREG bit 7/8 RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word causing the OERR (Overrun) bit to be set.
PIC18F1230/1330 15.2.4.1 Special Considerations Using Auto-Wake-up 15.2.4.2 Since auto-wake-up functions by sensing rising edge transitions on RX/DT, information with any state changes before the Stop bit may signal a false End-of-Character and cause data or framing errors. To work properly, therefore, the initial characters in the transmission must be all ‘0’s. This can be 00h (8 bits) for standard RS-232 devices or 000h (12 bits) for LIN/J2602 bus.
PIC18F1230/1330 15.2.5 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN/J2602 bus standard. The Break character transmit consists of a Start bit, followed by twelve ‘0’ bits and a Stop bit. The Frame Break character is sent whenever the SENDB and TXEN bits (TXSTA<3> and TXSTA<5>) are set while the Transmit Shift register is loaded with data.
PIC18F1230/1330 15.3 Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG is empty and the TXIF flag bit (PIR1<4>) is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXIE (PIE1<4>). TXIF is set regardless of the state of enable bit, TXIE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREG register.
PIC18F1230/1330 FIGURE 15-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RA3/RX/DT pin bit 0 bit 1 bit 2 bit 7 bit 6 RA2/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 15-7: Name INTCON REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INT0IE RBIE TMR0IF INT0IF RBIF 47 PIR1 — ADIF RCIF TXIF CMP2IF CMP1IF CMP0IF TMR1IF 49 PIE1 — ADIE RCIE TXIE CMP2IE
PIC18F1230/1330 15.3.2 EUSART SYNCHRONOUS MASTER RECEPTION 4. Enable the synchronous master serial port by setting bits, SYNC, SPEN and CSRC. 5. Ensure bits, CREN and SREN, are clear. 6. If the signal from the CK pin is to be inverted, set the TXCKP bit. 7. If interrupts are desired, set enable bit, RCIE. 8. If 9-bit reception is desired, set bit, RX9. 9. If a single reception is required, set bit, SREN. For continuous reception, set bit, CREN. 10.
PIC18F1230/1330 15.4 To set up a Synchronous Slave Transmission: EUSART Synchronous Slave Mode 1. Synchronous Slave mode is entered by clearing bit, CSRC (TXSTA<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 15.4.
PIC18F1230/1330 15.4.2 EUSART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep, or any Idle mode and bit SREN, which is a “don’t care” in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode.
PIC18F1230/1330 16.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The Analog-to-Digital (A/D) Converter module has 4 inputs for the 18/20/28-pin devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number in PIC18F1230/ 1330 devices. The ADCON0 register, shown in Register 16-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 16-2, configures the functions of the port pins.
PIC18F1230/1330 REGISTER 16-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source) 1 = Positive reference for the A/D is VREF+ 0 = Positive reference for the A/D is AVDD bit 3 PCFG
PIC18F1230/1330 REGISTER 16-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits 111 = 20 TAD 110 =
PIC18F1230/1330 The analog reference voltage is software selectable to the device’s positive supply voltage (VDD), or the voltage level on the RA4/T0CKI/AN2/VREF+ pin. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. The A/D Converter has a unique feature of being able to operate while the device is in Sleep mode.
PIC18F1230/1330 Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared OR • Waiting for the A/D interrupt Read A/D Result registers (ADRESH:ADRESL); clear bit ADIF, if required. For next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before the next acquisition starts. 6. 7. FIGURE 16-2: The following steps should be followed to perform an A/ D conversion: 3FFh 1.
PIC18F1230/1330 16.1 Triggering A/D Conversions The A/D conversion can be triggered by setting the GO/ DONE bit. This bit can either be set manually by the programmer or by setting the SEVTEN bit of ADCON0. When the SEVTEN bit is set, the Special Event Trigger from the Power Control PWM module triggers the A/D conversion. For more information, see Section 14.14 “PWM Special Event Trigger”. 16.
PIC18F1230/1330 16.3 Selecting and Configuring Acquisition Time 16.4 Selecting the A/D Conversion Clock The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. It also gives users the option to use an automatically determined acquisition time. The A/D conversion time per bit is defined as TAD. The A/D conversion requires 11 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable.
PIC18F1230/1330 16.5 Operation in Power-Managed Modes The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device is in a power-managed mode, the ACQT2:ACQT0 and ADCS2:ADCS0 bits in ADCON2 should be updated in accordance with the clock source to be used in that mode. After entering the mode, an A/D acquisition or conversion may be started.
PIC18F1230/1330 16.7 After the A/D conversion is completed or aborted, a 2 TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. A/D Conversions Figure 16-4 shows the operation of the A/D Converter after the GO/DONE bit has been set and the ACQT2:ACQT0 bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins.
PIC18F1230/1330 TABLE 16-2: Name INTCON REGISTERS ASSOCIATED WITH A/D OPERATION Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47 PIR1 — ADIF RCIF TXIF CMP2IF CMP1IF CMP0IF TMR1IF 49 PIE1 — ADIE RCIE TXIE CMP2IE CMP1IE CMP0IE TMR1IE 49 — ADIP RCIP TXIP CMP2IP CMP1IP CMP0IP TMR1IP IPR1 GIE/GIEH PEIE/GIEL Bit 5 ADRESH A/D Result Register High Byte ADRESL A/D Result Register Low Byte ADCON0 SEVTEN — 49
PIC18F1230/1330 17.0 COMPARATOR MODULE The analog comparator module contains three comparators. The inputs can be selected from the analog inputs multiplexed with pins RA0, RB2 and RB3, as well as the on-chip voltage reference (see REGISTER 17-1: Section 18.0 “Comparator Voltage Reference Module”). The digital outputs are not available at the pin level and can only be read through the control register, CMCON (Register 17-1). CMCON also selects the comparator input.
PIC18F1230/1330 17.1 Comparator Configuration For every analog comparator, there is a control bit called CMENx in the CMCON register. By setting the CMENx bit, the corresponding comparator can be enabled. If the Comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Section 23.0 “Electrical Characteristics”. Note 1: When reading the PORT register, all pins configured as analog inputs will read as a ‘0’.
PIC18F1230/1330 17.7 Comparator Operation During Sleep 17.9 When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional if enabled. This interrupt will wake-up the device from Sleep mode when enabled. Each operational comparator will consume additional current, as shown in the comparator specifications. To minimize power consumption while in Sleep mode, turn off the comparators (CMEN2:CMEN0 = 000) before entering Sleep.
PIC18F1230/1330 TABLE 17-1: Name CMCON CVRCON INTCON REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 C2OUT C1OUT C0OUT CVREN — CVRR TMR0IE INT0IE GIE/GIEH PEIE/GIEL Bit 4 Reset Values on Page: Bit 3 Bit 2 Bit 1 Bit 0 — — CMEN2 CMEN1 CMEN0 48 CVRSS CVR3 CVR2 CVR1 CVR0 48 RBIE TMR0IF INT0IF RBIF 47 PIR1 — ADIF RCIF TXIF CMP2IF CMP1IF CMP0IF TMR1IF 49 PIE1 — ADIE RCIE TXIE CMP2IE CMP1IE CMP0IE TMR1IE 49 49 IPR1 PORTA — ADIP RCIP TXIP CMP
PIC18F1230/1330 18.0 COMPARATOR VOLTAGE REFERENCE MODULE The comparator voltage reference is a 16-tap resistor ladder network that provides a selectable reference voltage. Its purpose is to provide a reference for the analog comparators. A block diagram of the module is shown in Figure 18-1. The resistor ladder is segmented to provide two ranges of CVREF values and has a power-down function to conserve power when the reference is not being used.
PIC18F1230/1330 REGISTER 18-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN — CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 Unimplemented: Read as ‘0’ b
PIC18F1230/1330 FIGURE 18-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ AVDD CVRSS = 1 8R CVRSS = 0 CVR3:CVR0 R CVREN R R 16-to-1 MUX R 16 Steps R CVREN = 0 CVREN = 1 CVREF R R CVRR 8R AVSS 18.2 CVRSS = x Voltage Reference Accuracy/Error The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 18-1) keep CVREF from approaching the reference source rails.
PIC18F1230/1330 NOTES: DS39758D-page 186 2009 Microchip Technology Inc.
PIC18F1230/1330 19.0 The Low-Voltage Detect Control register (Register 19-1) completely controls the operation of the LVD module. This allows the circuitry to be “turned off” by the user under software control, which minimizes the current consumption for the device. LOW-VOLTAGE DETECT (LVD) PIC18F1230/1330 devices have a Low-Voltage Detect module (LVD). This is a programmable circuit that allows the user to specify the device voltage trip point.
PIC18F1230/1330 The module is enabled by setting the LVDEN bit. Each time that the LVD module is enabled, the circuitry requires some time to stabilize. The IRVST bit is a read-only bit and is used to indicate when the circuit is stable. The module can only generate an interrupt after the circuit is stable and IRVST is set. 19.1 trip point voltage. The “trip point” voltage is the voltage level at which the device detects a low-voltage event depending on the configuration of the module.
PIC18F1230/1330 19.2 Depending on the application, the LVD module does not need to be operating constantly. To decrease the current requirements, the LVD circuitry may only need to be enabled for short periods where the voltage is checked. After doing the check, the LVD module may be disabled. LVD Setup The following steps are needed to set up the LVD module: 1. 2. 3. 4. 5. Disable the module by clearing the LVDEN bit (LVDCON<4>).
PIC18F1230/1330 19.5 Applications 19.6 In many applications, the ability to detect a drop below a particular threshold is desirable. For general battery applications, Figure 19-3 shows a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage VA, the LVD logic generates an interrupt at time TA.
PIC18F1230/1330 20.0 SPECIAL FEATURES OF THE CPU PIC18F1230/1330 devices include several features intended to maximize reliability and minimize cost through elimination of external components.
PIC18F1230/1330 REGISTER 20-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-0 R/P-0 U-0 U-0 R/P-0 R/P-1 R/P-1 R/P-1 IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode enabled 0 = Oscillator Switchover mode disabled bit 6
PIC18F1230/1330 REGISTER 20-2: U-0 CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 — — U-0 — R/P-1 BORV1 (1) R/P-1 BORV0 (1) R/P-1 R/P-1 (2) BOREN1 BOREN0 bit 7 R/P-1 (2) PWRTEN(2) bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-5 Unimplemented: Read as ‘0’ bit 4-3 BORV1:BORV0: Brown-out Reset Voltage bits(1) 11 = Minimum setting • • • 00 = Maximum
PIC18F1230/1330 REGISTER 20-3: U-0 CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 — — U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1
PIC18F1230/1330 REGISTER 20-4: U-0 CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300005h) U-0 — — U-0 — U-0 — R/P-1 HPOL (1) R/P-1 LPOL (1) R/P-1 U-0 PWMPIN — bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-4 Unimplemented: Read as ‘0’ bit 3 HPOL: High Side Transistors Polarity bit (Odd PWM Output Polarity Control bit)(1) 1 = PWM1, PWM3 and PWM5 are acti
PIC18F1230/1330 REGISTER 20-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 U-0 U-0 U-0 R/P-0 U-0 U-0 R/P-1 MCLRE — — — T1OSCMX — — FLTAMX bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled, RA5 input pin disabled 0 = RA5 input pin enabled, MCLR pin disabled bit 6-4 Unimplemented: Read as
PIC18F1230/1330 REGISTER 20-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 R/P-0 R/P-0 R/P-0 U-0 U-0 U-0 R/P-1 BKBUG XINST BBSIZ1 BBSIZ0 — — — STVREN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7 BKBUG: Background Debugger Enable bit 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background d
PIC18F1230/1330 REGISTER 20-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1 — — — — — — CP1 CP0 bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-2 Unimplemented: Read as ‘0’ bit 1 CP1: Code Protection bit (Block 1 Code Memory Area) 1 = Block 1 is not code-protected 0 = Block 1 is code-protected bit 0 CP0:
PIC18F1230/1330 REGISTER 20-9: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1 — — — — — — WRT1 WRT0 bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-2 Unimplemented: Read as ‘0’ bit 1 WRT1: Write Protection bit (Block 1 Code Memory Area) 1 = Block 1 is not write-protected 0 = Block 1 is write-protected bit 0
PIC18F1230/1330 REGISTER 20-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1 — — — — — — EBTR1(1) EBTR0(1) bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed u = Unchanged from programmed state bit 7-2 Unimplemented: Read as ‘0’ bit 1 EBTR1: Table Read Protection bit (Block 1 Code Memory Area) 1 = Block 1 is not protected from table reads executed in ot
PIC18F1230/1330 REGISTER 20-13: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F1230/1330 DEVICES R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Read-only bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-5 DEV2:DEV0: Device ID bits 000 = PIC18F1230 001 = PIC18F1330 bit 4-0 REV3:REV0: Revision ID bits These bits are used to indicate the device revision.
PIC18F1230/1330 20.2 Watchdog Timer (WDT) For PIC18F1230/1330 devices, the WDT is driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configuration Register 2H. Available periods range from 4 ms to 131.072 seconds (2.18 minutes).
PIC18F1230/1330 REGISTER 20-15: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — SWDTEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 Unimplemented: Read as ‘0’ bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off Note 1: This bit has no effect if the Configuration bit, WD
PIC18F1230/1330 20.3 In all other power-managed modes, Two-Speed Start-up is not used. The device will be clocked by the currently selected clock source until the primary clock source becomes available. The setting of the IESO bit is ignored. Two-Speed Start-up The Two-Speed Start-up feature helps to minimize the latency period from oscillator start-up to code execution by allowing the microcontroller to use the INTOSC oscillator as a clock source until the primary clock source is available.
PIC18F1230/1330 20.4 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block. The FSCM function is enabled by setting the FCMEN Configuration bit. When FSCM is enabled, the INTRC oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure.
PIC18F1230/1330 FIGURE 20-4: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure Device Clock Output CM Output (Q) Failure Detected OSCFIF CM Test Note: 20.4.3 CM Test The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. FSCM INTERRUPTS IN POWER-MANAGED MODES By entering a power-managed mode, the clock multiplexer selects the clock source selected by the OSCCON register.
PIC18F1230/1330 20.5 Each of the three blocks has three code protection bits associated with them. They are: Program Verification and Code Protection The overall structure of the code protection on the PIC18 Flash devices differs significantly from other PIC® devices. • Code-Protect bit (CPx) • Write-Protect bit (WRTx) • External Block Table Read bit (EBTRx) The user program memory is divided into three blocks. One of these is a Boot Block of variable size (maximum 2 Kbytes).
PIC18F1230/1330 20.5.1 PROGRAM MEMORY CODE PROTECTION The program memory may be read to or written from any location using the table read and table write instructions. The Device ID may be read with table reads. The Configuration registers may be read and written with the table read and table write instructions. A table read instruction that executes from a location outside of that block is not allowed to read and will result in reading ‘0’s.
PIC18F1230/1330 FIGURE 20-7: EXTERNAL BLOCK TABLE READ (EBTRx) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0007FFh 000800h TBLPTR = 0008FFh PC = 001100h WRTB, EBTRB = 11 WRT0, EBTR0 = 10 TBLRD* 000FFFh 001000h WRT1, EBTR1 = 11 001FFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRx = 0. TABLAT register returns a value of ‘0’.
PIC18F1230/1330 20.5.2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits internal and external writes to data EEPROM. The CPU can always read data EEPROM under normal operation, regardless of the protection bit settings. 20.5.3 CONFIGURATION REGISTER PROTECTION The Configuration registers can be write-protected.
PIC18F1230/1330 21.0 DEVELOPMENT SUPPORT 21.
PIC18F1230/1330 21.2 MPASM Assembler 21.5 The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
PIC18F1230/1330 21.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 21.9 The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
PIC18F1230/1330 21.11 PICSTART Plus Development Programmer 21.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
PIC18F1230/1330 22.0 INSTRUCTION SET SUMMARY PIC18F1230/1330 devices incorporate the standard set of 75 PIC18 core instructions, as well as an extended set of 8 new instructions for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 22.
PIC18F1230/1330 TABLE 22-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
PIC18F1230/1330 FIGURE 22-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 OPCODE Example Instruction 8 7 d 0 a f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 0 OPCODE 15 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE #)
PIC18F1230/1330 TABLE 22-2: PIC18FXXXX INSTRUCTION SET Mnemonic, Operands 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED OPERATIONS Add WREG and f Add WREG and Carry bit to f AND WREG with f Clear f Complement f Compare f with WREG, Skip = Compare f with WREG, Skip > Compare f with WREG, Skip < Decrement f Decrement f, Skip if 0 Decrement f, Skip if Not 0 Increment f Increment f, Skip if 0 Increment f, Skip if Not 0 Inclusive OR WREG with f Move f Move fs (sou
PIC18F1230/1330 TABLE 22-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG f, b, a f, b, a f, b, a f, b, a f, d, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None 1 (2) 1 (2
PIC18F1230/1330 TABLE 22-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add Literal and WREG AND Literal with WREG Inclusive OR Literal with WREG Move Literal (12-bit) 2nd word to FSR(f) 1st word Move Literal to BSR<3:0> Move Literal to WREG Multiply Literal with WREG Return with Literal in WREG Subtract WREG f
PIC18F1230/1330 22.1.1 STANDARD INSTRUCTION SET ADDLW ADD Literal to W ADDWF ADD W to f Syntax: ADDLW Syntax: ADDWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) + (f) dest Status Affected: N, OV, C, DC, Z k Operands: 0 k 255 Operation: (W) + k W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
PIC18F1230/1330 ADDWFC ADD W and Carry bit to f ANDLW Syntax: ADDWFC Syntax: ANDLW Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 k 255 Operation: (W) .AND. k W Status Affected: N, Z f {,d {,a}} Operation: (W) + (f) + (C) dest Status Affected: N,OV, C, DC, Z Encoding: 0010 Description: 00da Encoding: ffff ffff Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’.
PIC18F1230/1330 ANDWF AND W with f BC Branch if Carry Syntax: ANDWF Syntax: BC Operands: 0 f 255 d [0,1] a [0,1] Operands: -128 n 127 Operation: if Carry bit is ‘1’, (PC) + 2 + 2n PC Status Affected: None f {,d {,a}} Operation: (W) .AND. (f) dest Status Affected: N, Z Encoding: 0001 Description: Encoding: 01da ffff ffff The contents of W are ANDed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC18F1230/1330 BCF Bit Clear f BN Branch if Negative Syntax: BCF Syntax: BN Operands: 0 f 255 0b7 a [0,1] Operands: -128 n 127 Operation: if Negative bit is ‘1’, (PC) + 2 + 2n PC Status Affected: None f, b {,a} Operation: 0 f Status Affected: None Encoding: Encoding: 1001 Description: bbba ffff ffff Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
PIC18F1230/1330 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC Syntax: BNN n n Operands: -128 n 127 Operands: -128 n 127 Operation: if Carry bit is ‘0’, (PC) + 2 + 2n PC Operation: if Negative bit is ‘0’, (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn Description: If the Carry bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC.
PIC18F1230/1330 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV Syntax: BNZ Operands: -128 n 127 Operands: -128 n 127 Operation: if Overflow bit is ‘0’, (PC) + 2 + 2n PC Operation: if Zero bit is ‘0’, (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: n 1110 Description: 0101 nnnn nnnn Encoding: 1110 If the Overflow bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC.
PIC18F1230/1330 BRA Unconditional Branch BSF Syntax: BRA Syntax: BSF Operands: -1024 n 1023 Operands: 0 f 255 0b7 a [0,1] n Operation: (PC) + 2 + 2n PC Status Affected: None Encoding: 1101 Description: 0nnn nnnn nnnn Add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction.
PIC18F1230/1330 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 f 255 0b7 a [0,1] Operands: 0 f 255 0b<7 a [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 1011 Description: bbba ffff ffff Encoding: 1010 If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped.
PIC18F1230/1330 BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV Operands: 0 f 255 0b<7 a [0,1] Operands: -128 n 127 Operation: if Overflow bit is ‘1’, (PC) + 2 + 2n PC Status Affected: None Operation: (f) f Status Affected: None Encoding: 0111 Description: Words: Cycles: Encoding: bbba ffff ffff Bit ‘b’ in data memory location ‘f’ is inverted. If ‘a’ is ‘0’, the Access Bank is selected.
PIC18F1230/1330 BZ Branch if Zero CALL Subroutine Call Syntax: BZ Syntax: CALL k {,s} Operands: -128 n 127 Operands: Operation: if Zero bit is ‘1’, (PC) + 2 + 2n PC 0 k 1048575 s [0,1] Operation: (PC) + 4 TOS, k PC<20:1>; if s = 1, (W) WS, (STATUS) STATUSS, (BSR) BSRS Status Affected: None Status Affected: n None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is ‘1’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC.
PIC18F1230/1330 CLRF Clear f Syntax: CLRF Operands: 0 f 255 a [0,1] Operation: 000h f, 1Z Status Affected: Z Encoding: f {,a} 0110 Description: 101a ffff ffff Clears the contents of the specified register. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.
PIC18F1230/1330 COMF Complement f CPFSEQ Compare f with W, Skip if f = W Syntax: COMF Syntax: CPFSEQ Operands: 0 f 255 a [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None f {,d {,a}} 0 f 255 d [0,1] a [0,1] Operands: Operation: (f) dest Status Affected: N, Z Encoding: 0001 11da ffff ffff Description: The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W.
PIC18F1230/1330 CPFSGT Compare f with W, Skip if f > W CPFSLT Compare f with W, Skip if f < W Syntax: CPFSGT Syntax: CPFSLT Operands: 0 f 255 a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) –W), skip if (f) > (W) (unsigned comparison) Operation: (f) –W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 Description: Words: f {,a} 010a ffff ffff Compares the contents of data memory location ‘f’ to the contents of th
PIC18F1230/1330 DAW Decimal Adjust W Register DECF Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: Operation: If [W<3:0> > 9] or [DC = 1] then, (W<3:0>) + 6 W<3:0>; else, (W<3:0>) W<3:0> 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest Status Affected: C, DC, N, OV, Z If [W<7:4> + DC > 9] or [C = 1] then, (W<7:4>) + 6 + DC W<7:4>; else, (W<7:4>) + DC W<7:4> Status Affected: Decrement f Encoding: 0000 0000 0000 DAW adjusts the eight-bit value in W result
PIC18F1230/1330 DECFSZ Decrement f, Skip if 0 DCFSNZ Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest, skip if result = 0 Operation: (f) – 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0010 Description: 11da ffff ffff The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W.
PIC18F1230/1330 GOTO Unconditional Branch INCF Syntax: GOTO k Syntax: INCF Operands: 0 k 1048575 Operands: Operation: k PC<20:1> Status Affected: None 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 Description: 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 GOTO allows an unconditional branch Increment f Encoding: 0010 2 Cycles: 2 Q1 Q2 Q3 Q4 Read literal ‘k’<7:0>, No operation
PIC18F1230/1330 INCFSZ Increment f, Skip if 0 INFSNZ Syntax: INCFSZ Syntax: INFSNZ 0 f 255 d [0,1] a [0,1] f {,d {,a}} Increment f, Skip if Not 0 f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: Operation: (f) + 1 dest, skip if result = 0 Operation: (f) + 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0011 Description: 11da ffff ffff The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in W.
PIC18F1230/1330 IORLW Inclusive OR Literal with W IORWF Syntax: IORLW k Syntax: IORWF Operands: 0 k 255 Operands: Operation: (W) .OR. k W Status Affected: N, Z 0 f 255 d [0,1] a [0,1] Operation: (W) .OR. (f) dest Status Affected: N, Z Encoding: 0000 Description: 1001 kkkk kkkk The contents of W are ORed with the eight-bit literal ‘k’. The result is placed in W.
PIC18F1230/1330 LFSR Load FSR MOVF Syntax: LFSR f, k Syntax: MOVF Operands: 0f2 0 k 4095 Operands: Operation: k FSRf 0 f 255 d [0,1] a [0,1] Status Affected: None Operation: f dest Status Affected: N, Z Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the File Select Register pointed to by ‘f’.
PIC18F1230/1330 MOVFF Move f to f MOVLB Move Literal to Low Nibble in BSR Syntax: MOVFF fs,fd Syntax: MOVLW k Operands: 0 fs 4095 0 fd 4095 Operands: 0 k 255 Operation: k BSR Operation: (fs) fd Status Affected: None Status Affected: None Encoding: Encoding: 1st word (source) 2nd word (destin.) 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register ‘fs’ are moved to destination register ‘fd’.
PIC18F1230/1330 MOVLW Move Literal to W MOVWF Syntax: MOVLW k Syntax: MOVWF Operands: 0 k 255 Operands: Operation: kW 0 f 255 a [0,1] Status Affected: None Operation: (W) f Status Affected: None Encoding: 0000 1110 kkkk kkkk Description: The eight-bit literal ‘k’ is loaded into W. Words: 1 Cycles: 1 Move W to f Encoding: 0110 Q1 Q2 Q3 Q4 Read literal ‘k’ Process Data Write to W Example: MOVLW = ffff ffff Move data from W to register ‘f’.
PIC18F1230/1330 MULLW Multiply Literal with W MULWF Multiply W with f Syntax: MULLW Syntax: MULWF Operands: 0 k 255 Operands: Operation: (W) x k PRODH:PRODL 0 f 255 a [0,1] Status Affected: None Operation: (W) x (f) PRODH:PRODL Status Affected: None Encoding: 0000 Description: k 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in the PRODH:PRODL register pair.
PIC18F1230/1330 NEGF Negate f NOP No Operation Syntax: NEGF Syntax: NOP Operands: 0 f 255 a [0,1] Operands: None Operation: (f) + 1 f Status Affected: N, OV, C, DC, Z Encoding: f {,a} 0110 Description: 1 Cycles: 1 No operation Status Affected: None Encoding: 110a ffff 0000 1111 ffff Location ‘f’ is negated using two’s complement. The result is placed in the data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected.
PIC18F1230/1330 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) bit bucket Operation: (PC + 2) TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
PIC18F1230/1330 RCALL Relative Call RESET Reset Syntax: RCALL Syntax: RESET Operands: -1024 n 1023 Operands: None Operation: (PC) + 2 TOS, (PC) + 2 + 2n PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: n 1101 Description: 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack.
PIC18F1230/1330 RETFIE Return from Interrupt RETLW Return Literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s [0,1] Operands: 0 k 255 Operation: (TOS) PC, 1 GIE/GIEH or PEIE/GIEL; if s = 1, (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged Operation: k W, (TOS) PC, PCLATU, PCLATH are unchanged Status Affected: None Status Affected: 0000 0000 0001 1 Cycles: 2 Q Cycle Activity: Q2 Q3 Q4 Decode No operation No operation POP PC from sta
PIC18F1230/1330 RETURN Return from Subroutine RLCF Syntax: RETURN {s} Syntax: RLCF Operands: s [0,1] Operands: Operation: (TOS) PC; if s = 1, (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) C, (C) dest<0> Status Affected: C, N, Z Status Affected: None Encoding: 0000 Rotate Left f through Carry Encoding: 0000 0001 001s Description: Return from subroutine.
PIC18F1230/1330 RLNCF Rotate Left f (No Carry) RRCF Syntax: RLNCF Syntax: RRCF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) dest<0> Operation: Status Affected: N, Z (f) dest, (f<0>) C, (C) dest<7> Status Affected: C, N, Z Encoding: 0100 Description: f {,d {,a}} 01da ffff ffff The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result is placed in W.
PIC18F1230/1330 RRNCF Rotate Right f (No Carry) SETF Syntax: RRNCF Syntax: SETF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 a [0,1] Operation: FFh f Operation: (f) dest, (f<0>) dest<7> Status Affected: None Status Affected: f {,d {,a}} Encoding: N, Z Encoding: 0100 Description: 00da ffff ffff The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W.
PIC18F1230/1330 SLEEP Enter Sleep mode SUBFWB Syntax: SLEEP Syntax: SUBFWB Operands: None Operands: Operation: 00h WDT, 0 WDT postscaler, 1 TO, 0 PD 0 f 255 d [0,1] a [0,1] Operation: (W) – (f) – (C) dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Encoding: 0000 0000 0011 Description: The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set. Watchdog Timer and its postscaler are cleared.
PIC18F1230/1330 SUBLW Subtract W from Literal SUBWF Syntax: SUBLW k Syntax: SUBWF Operands: 0 k 255 Operands: Operation: k – (W) W Status Affected: N, OV, C, DC, Z 0 f 255 d [0,1] a [0,1] Operation: (f) – (W) dest Status Affected: N, OV, C, DC, Z Encoding: 0000 Description 1000 kkkk kkkk W is subtracted from the eight-bit literal ‘k’. The result is placed in W.
PIC18F1230/1330 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB Syntax: SWAPF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – (W) – (C) dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> Status Affected: None Encoding: 0101 Description: f {,d {,a}} 10da ffff ffff Subtract W and the Carry flag (borrow) from register ‘f’ (2’s complement method).
PIC18F1230/1330 TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example 1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) TABLAT, TBLPTR – No Change; if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT, (TBLPTR) + 1 TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT, (TBLPTR) – 1 TBLPTR; if TBLRD +*, (TBLPTR) + 1 TBLPTR, (Prog Mem (TBLPTR)) TABLAT Example 2: 0000 0000 0000 TBLRD = = = 55h 00A356h 34h = = 34h 00A357h +* ; Before Instruction T
PIC18F1230/1330 TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example 1: TBLWT *+; Operands: None Operation: if TBLWT*, (TABLAT) Holding Register, TBLPTR – No Change; if TBLWT*+, (TABLAT) Holding Register, (TBLPTR) + 1 TBLPTR; if TBLWT*-, (TABLAT) Holding Register, (TBLPTR) – 1 TBLPTR; if TBLWT+*, (TBLPTR) + 1 TBLPTR, (TABLAT) Holding Register Status Affected: Before Instruction TABLAT = 55h TBLPTR = 00A356h HOLDING REGISTER (00A356h) = FFh After I
PIC18F1230/1330 TSTFSZ Test f, Skip if 0 XORLW Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 f 255 a [0,1] Operands: 0 k 255 Operation: (W) .XOR. k W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: Encoding: 0110 Description: Exclusive OR Literal with W 011a ffff ffff If ‘f’ = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction.
PIC18F1230/1330 XORWF Exclusive OR W with f Syntax: XORWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 f {,d {,a}} 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
PIC18F1230/1330 22.2 A summary of the instructions in the extended instruction set is provided in Table 22-3. Detailed descriptions are provided in Section 22.2.2 “Extended Instruction Set”. The opcode field descriptions in Table 22-1 (page 216) apply to both the standard and extended PIC18 instruction sets. Extended Instruction Set In addition to the standard 75 instructions of the PIC18 instruction set, PIC18F1230/1330 devices also provide an optional extension to the core CPU functionality.
PIC18F1230/1330 22.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 k 63 f [ 0, 1, 2 ] Operands: 0 k 63 Operation: Operation: FSR(f) + k FSR(f) FSR2 + k FSR2, (TOS) PC Status Affected: None Status Affected: None Encoding: 1110 1000 ffkk kkkk Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’.
PIC18F1230/1330 CALLW Subroutine Call Using WREG MOVSF Syntax: CALLW Syntax: MOVSF [zs], fd Operands: None Operands: Operation: (PC + 2) TOS, (W) PCL, (PCLATH) PCH, (PCLATU) PCU 0 zs 127 0 fd 4095 Operation: ((FSR2) + zs) fd Status Affected: None Status Affected: None Encoding: 0000 0000 0001 0100 Description First, the return address (PC + 2) is pushed onto the return stack. Next, the contents of W are written to PCL; the existing value is discarded.
PIC18F1230/1330 MOVSS Move Indexed to Indexed PUSHL Syntax: Syntax: PUSHL k Operands: MOVSS [zs], [zd] 0 zs 127 0 zd 127 Operands: 0k 255 Operation: ((FSR2) + zs) ((FSR2) + zd) Operation: k (FSR2), FSR2 – 1 FSR2 Status Affected: None Status Affected: None Encoding: 1st word (source) 2nd word (dest.) 1110 1111 Description 1011 xxxx 1zzz xzzz zzzzs zzzzd The contents of the source register are moved to the destination register.
PIC18F1230/1330 SUBFSR Subtract Literal from FSR SUBULNK Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 k 63 Operands: 0 k 63 f [ 0, 1, 2 ] Operation: Operation: FSR(f – k) FSR(f) Status Affected: None Encoding: 1110 Description: 1001 ffkk 1 Cycles: 1 FSR2 – k FSR2, (TOS) PC kkkk The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘f’.
PIC18F1230/1330 22.2.3 Note: BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing mode (Section 6.5.1 “Indexed Addressing with Literal Offset”).
PIC18F1230/1330 ADDWF ADD W to Indexed (Indexed Literal Offset mode) BSF Bit Set Indexed (Indexed Literal Offset mode) Syntax: ADDWF Syntax: BSF [k], b Operands: 0 k 95 d [0,1] Operands: 0 f 95 0b7 Operation: (W) + ((FSR2) + k) dest Operation: 1 ((FSR2) + k) Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: [k] {,d} 0010 Description: 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offset by the value ‘
PIC18F1230/1330 22.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB® IDE TOOLS The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set of the PIC18F1230/1330 family of devices. This includes the MPLAB C18 C Compiler, MPASM Assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device.
PIC18F1230/1330 23.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.
PIC18F1230/1330 FIGURE 23-1: PIC18F1230/1330 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz Frequency PIC18F1230/1330 VOLTAGE-FREQUENCY GRAPH (EXTENDED) FIGURE 23-2: 6.0V 5.5V Voltage 5.0V 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 25 MHz Frequency DS39758D-page 266 2009 Microchip Technology Inc.
PIC18F1230/1330 FIGURE 23-3: PIC18LF1230/1330 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz 4 MHz Frequency FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application. 2009 Microchip Technology Inc.
PIC18F1230/1330 23.1 DC Characteristics: Supply Voltage PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F1230/1330 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC18F1230/1330 23.2 DC Characteristics: Power-Down and Supply Current PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F1230/1330 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC18F1230/1330 23.2 DC Characteristics: Power-Down and Supply Current PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) (Continued) PIC18LF1230/1330 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F1230/1330 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC18F1230/1330 23.2 DC Characteristics: Power-Down and Supply Current PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) (Continued) PIC18LF1230/1330 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F1230/1330 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC18F1230/1330 23.2 DC Characteristics: Power-Down and Supply Current PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) (Continued) PIC18LF1230/1330 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F1230/1330 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC18F1230/1330 23.2 DC Characteristics: Power-Down and Supply Current PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) (Continued) PIC18LF1230/1330 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F1230/1330 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC18F1230/1330 23.2 DC Characteristics: Power-Down and Supply Current PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) (Continued) PIC18LF1230/1330 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F1230/1330 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC18F1230/1330 23.2 DC Characteristics: Power-Down and Supply Current PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) (Continued) PIC18LF1230/1330 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F1230/1330 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC18F1230/1330 23.2 DC Characteristics: Power-Down and Supply Current PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) (Continued) PIC18LF1230/1330 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F1230/1330 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC18F1230/1330 23.2 DC Characteristics: Power-Down and Supply Current PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) (Continued) PIC18LF1230/1330 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F1230/1330 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC18F1230/1330 23.2 DC Characteristics: Power-Down and Supply Current PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) (Continued) PIC18LF1230/1330 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18F1230/1330 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC18F1230/1330 23.3 DC Characteristics: PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Max Units Conditions VSS 0.15 VDD V VDD < 4.5V — 0.8 V 4.5V VDD 5.
PIC18F1230/1330 23.3 DC Characteristics: PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC CHARACTERISTICS Param Symbol No. VOL Characteristic Min Max Units Conditions Output Low Voltage D080 I/O ports — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C D083 OSC2/CLKO (RC, RCIO, EC, ECIO modes) — 0.6 V IOL = 1.6 mA, VDD = 4.
PIC18F1230/1330 TABLE 23-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC CHARACTERISTICS Param No. Sym Characteristic Min Typ† Max Units Conditions Data EEPROM Memory D120 ED Byte Endurance 100K 1M — D121 VDRW VDD for Read/Write VMIN — 5.5 E/W -40C to +85C V D122 TDEW Erase/Write Cycle Time 3.59 4.10 4.
PIC18F1230/1330 TABLE 23-2: COMPARATOR SPECIFICATIONS Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated). Param No. Sym Characteristics Min Typ Max Units Comments D300 VIOFF Input Offset Voltage — ±5.0 ±10 mV D301 VICM Input Common Mode Voltage 0 — VDD – 1.5 V D302 CMRR Common Mode Rejection Ratio 55 — — dB D303 TRESP Response Time(1) — 150 400 ns PIC18FXXXX — 150 600 ns PIC18LFXXXX, VDD = 2.
PIC18F1230/1330 FIGURE 23-4: LOW-VOLTAGE DETECT CHARACTERISTICS VDD (LVDIF can be cleared in software) VLVD (LVDIF set by hardware) LVDIF TABLE 23-4: LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. D420 Sym Characteristic Min Typ Max Units LVDL<3:0> = 0000 LVD Voltage on VDD Transition High-to-Low LVDL<3:0> = 0001 2.06 2.17 2.28 V 2.12 2.23 2.
PIC18F1230/1330 23.4 23.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 2.
PIC18F1230/1330 23.4.2 TIMING CONDITIONS Because of space limitations, the generic terms “PIC18FXXXX” and “PIC18LFXXXX” are used throughout this section to refer to the PIC18F1230/1330 and PIC18LF1230/ 1330 families of devices specifically and only those devices. Note: The temperature and voltages specified in Table 23-5 apply to all timing specifications unless otherwise noted. Figure 23-5 specifies the load conditions for the timing specifications.
PIC18F1230/1330 23.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 23-6: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 23-6: Param. No. 1A EXTERNAL CLOCK TIMING REQUIREMENTS Symbol FOSC Characteristic Min Max Units External CLKI Frequency(1) DC 1 MHz XT, RC Oscillator modes DC 40 MHz EC Oscillator mode DC 31.25 kHz LP Oscillator mode DC 4 MHz RC Oscillator mode 0.
PIC18F1230/1330 TABLE 23-7: Param No. PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V) Sym Characteristic Min Typ† Max 4 16 — — 10 40 Units F10 F11 FOSC Oscillator Frequency Range FSYS On-Chip VCO System Frequency F12 trc PLL Start-up Time (Lock Time) — — 2 ms CLK CLKO Stability (Jitter) -2 — +2 % F13 Conditions MHz HS mode only MHz HS mode only † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
PIC18F1230/1330 FIGURE 23-7: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 14 12 18 19 16 I/O pin (Input) 15 17 I/O pin (Output) New Value Old Value 20, 21 Refer to Figure 23-5 for load conditions. Note: TABLE 23-9: Param No.
PIC18F1230/1330 FIGURE 23-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 Oscillator Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure 23-5 for load conditions.
PIC18F1230/1330 FIGURE 23-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 23-5 for load conditions. TABLE 23-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No.
PIC18F1230/1330 FIGURE 23-11: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RA2/TX/CK pin 121 121 RA3/RX/DT pin 120 122 Refer to Figure 23-5 for load conditions. Note: TABLE 23-12: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
PIC18F1230/1330 TABLE 23-14: A/D CONVERTER CHARACTERISTICS Param Symbol No. Characteristic Min Typ Max Units — — 10 bit Conditions VREF 3.0V A01 NR Resolution A03 EIL Integral Linearity Error — — < ±1 LSb VREF 3.0V A04 EDL Differential Linearity Error — — < ±1 LSb VREF 3.0V A06 EOFF Offset Error — — < ±2 LSb VREF 3.0V A07 EGN Gain Error — — < ±1 LSb VREF 3.
PIC18F1230/1330 FIGURE 23-13: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK (1) 132 9 A/D DATA 8 7 ... ... 2 1 0 NEW_DATA OLD_DATA ADRES TCY ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
PIC18F1230/1330 NOTES: DS39758D-page 294 2009 Microchip Technology Inc.
PIC18F1230/1330 24.0 PACKAGING INFORMATION 24.1 Package Marking Information 18-Lead PDIP Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 18-Lead SOIC XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX PIC18F1330-I/P e3 0910017 Example PIC18F1230E/SO e3 0910017 YYWWNNN 20-Lead SSOP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 28-Lead QFN PIC18F1230E/SS e3 0910017 Example XXXXXXXX XXXXXXXX YYWWNNN Legend: XX...
PIC18F1230/1330 24.2 Package Details The following sections give the technical details of the packages. 18-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c A1 b1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 18 Pitch e Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .
PIC18F1230/1330 18-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 e b α h h c φ A2 A A1 β L L1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 18 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 2.05 – – Standoff § A1 0.10 – 0.
PIC18F1230/1330 ! '((### ( DS39758D-page 298 " # $ ! % ! & " 2009 Microchip Technology Inc.
PIC18F1230/1330 20-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 e b c A2 A φ A1 L1 Units Dimension Limits Number of Pins L MILLIMETERS MIN N NOM MAX 20 Pitch e Overall Height A – 0.65 BSC – 2.00 Molded Package Thickness A2 1.65 1.75 1.85 Standoff A1 0.05 – – Overall Width E 7.40 7.80 8.
PIC18F1230/1330 28-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6 mm Body [QFN] with 0.55 mm Contact Length Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D2 EXPOSED PAD e E b E2 2 2 1 1 N K N NOTE 1 L BOTTOM VIEW TOP VIEW A A3 A1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 28 Pitch e Overall Height A 0.80 0.65 BSC 0.90 1.00 Standoff A1 0.00 0.02 0.
PIC18F1230/1330 $ % &'(( ) * * % ! '((### ( 2009 Microchip Technology Inc.
PIC18F1230/1330 NOTES: DS39758D-page 302 2009 Microchip Technology Inc.
PIC18F1230/1330 APPENDIX A: REVISION HISTORY Updated Section 23.0 “Electrical Characteristics” and Section 24.0 “Packaging Information”. Revision A (November 2005) Original data sheet for PIC18F1230/1330 devices. Revision D (November 2009) Revision B (February 2006) Data bank information was updated and a note was added for calculating the PCPWM duty cycle. TABLE A-1: Revision C (March 2007) Updated LIN 1.2 to LIN/J2602 throughout document along with minor corrections throughout document.
PIC18F1230/1330 APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. TABLE B-1: DEVICE DIFFERENCES Features PIC18F1230 PIC18F1330 Program Memory (Bytes) 4096 8192 Program Memory (Instructions) 2048 4096 18-Pin PDIP 18-Pin SOIC 20-Pin SSOP 28-Pin QFN 18-Pin PDIP 18-Pin SOIC 20-Pin SSOP 28-Pin QFN Packages DS39758D-page 304 2009 Microchip Technology Inc.
PIC18F1230/1330 APPENDIX C: CONVERSION CONSIDERATIONS This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B. Not Applicable 2009 Microchip Technology Inc.
PIC18F1230/1330 APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the Enhanced devices (i.e., PIC18FXXX) is provided in AN716, “Migrating Designs from PIC16C74A/74B to PIC18C442”. The changes discussed, while device specific, are generally applicable to all mid-range to Enhanced device migrations.
PIC18F1230/1330 INDEX A A/D ................................................................................... 169 A/D Converter Interrupt, Configuring ....................... 173 Acquisition Requirements ........................................ 174 ADCON0 Register .................................................... 169 ADCON1 Register .................................................... 169 ADCON2 Register .................................................... 169 ADRESH Register ..........................
PIC18F1230/1330 How to Clear RAM (Bank 0) Using Indirect Addressing . 65 Implementing a Real-Time Clock Using a Timer1 Interrupt Service ...................................................... 115 Initializing PORTA ...................................................... 87 Initializing PORTB ...................................................... 90 Reading a Flash Program Memory Word .................. 75 Saving STATUS, WREG and BSR Registers in RAM ... 105 Writing to Flash Program Memory ...................
PIC18F1230/1330 Associated Registers, Transmit ....................... 165 Reception ......................................................... 166 Transmission ................................................... 164 Synchronous Slave Mode ........................................ 167 Associated Registers, Receive ........................ 168 Associated Registers, Transmit ....................... 167 Reception ......................................................... 168 Transmission .........................
PIC18F1230/1330 MOVLW ................................................................... 241 MOVWF ................................................................... 241 MULLW .................................................................... 242 MULWF .................................................................... 242 NEGF ....................................................................... 243 NOP .........................................................................
PIC18F1230/1330 Oscillator Transitions ......................................................... 27 Oscillator, Timer1 ............................................................. 111 P Packaging ........................................................................ 295 Details ...................................................................... 296 Marking Information ................................................. 295 PICSTART Plus Development Programmer .................... 214 PIE Registers ....
PIC18F1230/1330 Postscaler ................................................................ 125 Prescaler .................................................................. 125 Single-Shot Mode .................................................... 125 R RAM. See Data Memory. RBIF Bit .............................................................................. 90 RC Oscillator ...................................................................... 23 RCIO Oscillator Mode ....................................
PIC18F1230/1330 Timer1 .............................................................................. 111 16-Bit Read/Write Mode ........................................... 114 Associated Registers ............................................... 115 Interrupt .................................................................... 114 Operation ................................................................. 112 Oscillator ..........................................................
PIC18F1230/1330 NOTES: DS39758D-page 314 2009 Microchip Technology Inc.
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PIC18F1230/1330 PIC18F1230/1330 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device PIC18F1230/1330(1) PIC18F1230/1330T(2) VDD range 4.2V to 5.5V PIC18LF1230/1330(1) PIC18LF1230/1330T(2) VDD range 2.0V to 5.5V Temperature Range I E = = Package SO SS P ML = = = = Pattern PIC18LF1330-I/P 301 = Industrial temp.
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