Datasheet

PIC18F1230/1330
DS39758D-page 84  2009 Microchip Technology Inc.
8.7 Operation During Code-Protect
Data EEPROM memory has its own code-protect bits
in Configuration Words. External read and write
operations are disabled if either of these mechanisms
are enabled.
The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the
code-protect Configuration bit. Refer to Section 20.0
“Special Features of the CPU” for additional
information.
8.8 Using the Data EEPROM
The data EEPROM is a high-endurance, byte
addressable array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other data that are updated
often). Frequently changing values will typically be
updated more often than specification D124. If this is
not the case, an array refresh must be performed. For
this reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
Flash program memory.
A simple data EEPROM refresh routine is shown in
Example 8-3.
EXAMPLE 8-3: DATA EEPROM REFRESH ROUTINE
TABLE 8-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Note: If data EEPROM is only used to store
constants and/or data that changes rarely,
an array refresh is likely not required. See
specification D124.
CLRF EEADR ; Start at address 0
BCF EECON1, CFGS ; Set for memory
BCF EECON1, EEPGD ; Set for Data EEPROM
BCF INTCON, GIE ; Disable interrupts
BSF EECON1, WREN ; Enable writes
LOOP ; Loop to refresh array
BSF EECON1, RD ; Read current address
MOVLW 55h ;
Required MOVWF EECON2 ; Write 55h
Sequence MOVLW 0AAh ;
MOVWF EECON2 ; Write 0AAh
BSF EECON1, WR ; Set WR bit to begin write
BTFSC EECON1, WR ; Wait for write to complete
BRA $-2
INCFSZ EEADR, F ; Increment address
BRA LOOP ; Not zero, do it again
BCF EECON1, WREN ; Disable writes
BSF INTCON, GIE ; Enable interrupts
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values on
Page:
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47
EEADR EEPROM Address Register 49
EEDATA EEPROM Data Register 49
EECON2 EEPROM Control Register 2 (not a physical register) 49
EECON1 EEPGD CFGS
— FREE WRERR WREN WR RD 49
IPR2 OSCFIP — — EEIP — LVDIP — —49
PIR2
OSCFIF — — EEIF — LVDIF — —49
PIE2
OSCFIE — — EEIE — LVDIE — —49
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.