Datasheet

PIC18F1230/1330
 2009 Microchip Technology Inc. DS39758D-page 63
PTMRL PWM Time Base Register (lower 8 bits) 0000 0000 49, 125
PTMRH
— — — — PWM Time Base Register (upper 4 bits) ---- 0000 49, 125
PTPERL PWM Time Base Period Register (lower 8 bits) 1111 1111 49, 125
PTPERH
— — — — PWM Time Base Period Register (upper 4 bits) ---- 1111 49, 125
TRISB PORTB Data Direction Control Register 1111 1111 49, 90
TRISA TRISA7
(4)
TRISA6
(4)
PORTA Data Direction Control Register 1111 1111 49, 87
PDC0L PWM Duty Cycle #0L Register (lower 8 bits) 0000 0000 49, 131
PDC0H
— — PWM Duty Cycle #0H Register (upper 6 bits) --00 0000 49, 131
PDC1L PWM Duty Cycle #1L Register (lower 8 bits) 0000 0000 49, 131
PDC1H
— — PWM Duty Cycle #1H Register (upper 6 bits) --00 0000 49, 131
PDC2L PWM Duty Cycle #2L Register (lower 8 bits) 0000 0000 49, 131
PDC2H
— — PWM Duty Cycle #2H Register (upper 6 bits) --00 0000 49, 131
FLTCONFIG BRFEN
— — — — FLTAS FLTAMOD FLTAEN 0--- -000 49, 143
LATB PORTB Output Latch Register (Read and Write to Data Latch) xxxx xxxx 49, 90
LATA LATA7
(4)
LATA6
(4)
PORTA Output Latch Register (Read and Write to Data Latch) xxxx xxxx 49, 87
SEVTCMPL PWM Special Event Compare Register (lower 8 bits) 0000 0000 49, 144
SEVTCMPH
— — — — PWM Special Event Compare Register (upper 4 bits) ---- 0000 50, 144
PWMCON0
—PWMEN2
(6)
PWMEN1
(6)
PWMEN0
(6)
— PMOD2 PMOD1 PMOD0 -100 -000 50, 123
-000 -000
PWMCON1 SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0 SEVTDIR
— UDIS OSYNC 0000 0-00 50, 124
DTCON DTPS1 DTPS0 DT5 DT4 DT3 DT2 DT1 DT0 0000 0000 50, 136
OVDCOND
— — POVD5 POVD4 POVD3 POVD2 POVD1 POVD0 --11 1111 50, 140
OVDCONS
— — POUT5 POUT4 POUT3 POUT2 POUT1 POUT0 --00 0000 50, 140
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 50, 90
PORTA RA7
(4)
RA6
(4)
RA5
(3)
RA4 RA3 RA2 RA1 RA0 xx0x xxxx 50, 87
TABLE 6-2: REGISTER FILE SUMMARY (PIC18F1230/1330) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on
Page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads
as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”.
2: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See
Section 3.6.4 “PLL in INTOSC Modes”.
3: The RA5 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RA5 reads as
‘0’. This bit is read-only.
4: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
5: Bit 7 and bit 6 are cleared by user software or by a POR.
6: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L.
7: This bit has no effect if the Configuration bit, WDTEN, is enabled.