Datasheet

PIC18F1230/1330
DS39758D-page 48  2009 Microchip Technology Inc.
INDF2 1230 1330 N/A N/A N/A
POSTINC2 1230 1330 N/A N/A N/A
POSTDEC2 1230 1330 N/A N/A N/A
PREINC2 1230 1330 N/A N/A N/A
PLUSW2 1230 1330 N/A N/A N/A
FSR2H 1230 1330 ---- 0000 ---- 0000 ---- uuuu
FSR2L 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu
STATUS 1230 1330 ---x xxxx ---u uuuu ---u uuuu
TMR0H 1230 1330 0000 0000 0000 0000 uuuu uuuu
TMR0L 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu
T0CON 1230 1330 1111 1111 1111 1111 uuuu uuuu
OSCCON 1230 1330 0100 q000 0100 q000 uuuu uuqu
LVDCON 1230 1330 --00 0101 --00 0101 --uu uuuu
WDTCON 1230 1330 ---- ---0 ---- ---0 ---- ---u
RCON
(4)
1230 1330 0q-1 11q0 0q-q qquu uq-u qquu
TMR1H 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 1230 1330 0000 0000 u0uu uuuu uuuu uuuu
ADRESH 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 1230 1330 0--- 0000 0--- 0000 u--- uuuu
ADCON1 1230 1330 ---0 1111 ---0 1111 ---u uuuu
ADCON2 1230 1330 0-00 0000 0-00 0000 u-uu uuuu
BAUDCON 1230 1330 01-00 0-00 01-00 0-00 uu-uu u-uu
CVRCON 1230 1330 0-00 0000 0-00 0000 u-uu uuuu
CMCON 1230 1330 000- -000 000- -000 uuu- -uuu
SPBRGH 1230 1330 0000 0000 0000 0000 uuuu uuuu
SPBRG 1230 1330 0000 0000 0000 0000 uuuu uuuu
RCREG 1230 1330 0000 0000 0000 0000 uuuu uuuu
TXREG 1230 1330 0000 0000 0000 0000 uuuu uuuu
TXSTA 1230 1330 0000 0010 0000 0010 uuuu uuuu
RCSTA 1230 1330 0000 000x 0000 000x uuuu uuuu
TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable
Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 5-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
6: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L.