Datasheet
PIC18F1230/1330
2009 Microchip Technology Inc. DS39758D-page 47
TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Applicable
Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
TOSU 1230 1330 ---0 0000 ---0 0000 ---0 uuuu
(3)
TOSH 1230 1330 0000 0000 0000 0000 uuuu uuuu
(3)
TOSL 1230 1330 0000 0000 0000 0000 uuuu uuuu
(3)
STKPTR 1230 1330 00-0 0000 uu-0 0000 uu-u uuuu
(3)
PCLATU 1230 1330 ---0 0000 ---0 0000 ---u uuuu
PCLATH 1230 1330 0000 0000 0000 0000 uuuu uuuu
PCL 1230 1330 0000 0000 0000 0000 PC + 2
(2)
TBLPTRU 1230 1330 --00 0000 --00 0000 --uu uuuu
TBLPTRH 1230 1330 0000 0000 0000 0000 uuuu uuuu
TBLPTRL 1230 1330 0000 0000 0000 0000 uuuu uuuu
TABLAT 1230 1330 0000 0000 0000 0000 uuuu uuuu
PRODH 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu
PRODL 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu
INTCON 1230 1330 0000 000x 0000 000u uuuu uuuu
(1)
INTCON2 1230 1330 1111 1111 1111 1111 uuuu uuuu
(1)
INTCON3 1230 1330 1100 0000 1100 0000 uuuu uuuu
(1)
INDF0 1230 1330 N/A N/A N/A
POSTINC0 1230 1330 N/A N/A N/A
POSTDEC0 1230 1330 N/A N/A N/A
PREINC0 1230 1330 N/A N/A N/A
PLUSW0 1230 1330 N/A N/A N/A
FSR0H 1230 1330 ---- 0000 ---- 0000 ---- uuuu
FSR0L 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu
WREG 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 1230 1330 N/A N/A N/A
POSTINC1 1230 1330 N/A N/A N/A
POSTDEC1 1230 1330 N/A N/A N/A
PREINC1 1230 1330 N/A N/A N/A
PLUSW1 1230 1330 N/A N/A N/A
FSR1H 1230 1330 ---- 0000 ---- 0000 ---- uuuu
FSR1L 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu
BSR 1230 1330 ---- 0000 ---- 0000 ---- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 5-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
6: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L.