Datasheet

PIC18F1230/1330
 2009 Microchip Technology Inc. DS39758D-page 291
FIGURE 23-11: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 23-12: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 23-12: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 23-13: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
No.
Symbol Characteristic Min Max Units Conditions
120 TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid PIC18FXXXX — 40 ns
PIC18LFXXXX — 100 ns VDD = 2.0V
121 Tckrf Clock Out Rise Time and Fall Time
(Master mode)
PIC18FXXXX — 20 ns
PIC18LFXXXX — 50 ns V
DD = 2.0V
122 Tdtrf Data Out Rise Time and Fall Time PIC18FXXXX — 20 ns
PIC18LFXXXX — 50 ns VDD = 2.0V
Param.
No.
Symbol Characteristic Min Max Units Conditions
125 TdtV2ckl SYNC RCV (MASTER & SLAVE)
Data Hold before CK  (DT hold time) 10 — ns
126 TckL2dtl Data Hold after CK  (DT hold time) 15 — ns
121
121
120
122
RA2/TX/CK
RA3/RX/DT
pin
pin
Note: Refer to Figure 23-5 for load conditions.
125
126
RA2/TX/CK
RA3/RX/DT
pin
pin
Note: Refer to Figure 23-5 for load conditions.