Datasheet

PIC18F1230/1330
 2009 Microchip Technology Inc. DS39758D-page 165
FIGURE 15-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
TABLE 15-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
RA3/RX/DT pin
RA2/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
bit 0
bit 1
bit 2
bit 6
bit 7
TXEN bit
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47
PIR1 — ADIF RCIF TXIF CMP2IF CMP1IF CMP0IF TMR1IF 49
PIE1 — ADIE RCIE TXIE CMP2IE CMP1IE CMP0IE TMR1IE 49
IPR1
— ADIP RCIP TXIP CMP2IP CMP1IP CMP0IP TMR1IP 49
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 48
TXREG EUSART Transmit Register 48
TXSTA CSRC TX9 TXEN SYNC
SENDB BRGH TRMT TX9D 48
BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 48
SPBRGH EUSART Baud Rate Generator Register High Byte 48
SPBRG EUSART Baud Rate Generator Register Low Byte 48
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.