Datasheet

© 2007 Microchip Technology Inc. DS39605F-page 71
PIC18F1220/1320
8.0 8 x 8 HARDWARE MULTIPLIER
8.1 Introduction
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18F1220/1320 devices. By making the multiply
a hardware operation, it completes in a single instruc-
tion cycle. This is an unsigned multiply that gives a
16-bit result. The result is stored into the 16-bit product
register pair (PRODH:PRODL). The multiplier does not
affect any flags in the Status register.
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply
algorithms
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 8-1 shows a performance comparison between
Enhanced devices using the single-cycle hardware
multiply and performing the same function without the
hardware multiply.
TABLE 8-1: PERFORMANCE COMPARISON
8.2 Operation
Example 8-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 8-1: 8 x 8 UNSIGNED
MULTIPLY ROUTINE
EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY
ROUTINE
Routine Multiply Method
Program
Memory
(Words)
Cycles
(Max)
Time
@ 40 MHz @ 10 MHz @ 4 MHz
8 x 8 unsigned
Without hardware multiply 13 69 6.9 μs 27.6 μs69 μs
Hardware multiply 1 1 100 ns 400 ns 1 μs
8 x 8 signed
Without hardware multiply 33 91 9.1 μs 36.4 μs91 μs
Hardware multiply 6 6 600 ns 2.4 μs6 μs
16 x 16 unsigned
Without hardware multiply 21 242 24.2 μs 96.8 μs 242 μs
Hardware multiply 28 28 2.8 μs11.2 μs28 μs
16 x 16 signed
Without hardware multiply 52 254 25.4 μs 102.6 μs 254 μs
Hardware multiply 35 40 4 μs16 μs40 μs
MOVF ARG1, W ;
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
MOVF ARG1, W
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
BTFSC ARG2, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG1
MOVF ARG2, W
BTFSC ARG1, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG2