Datasheet

© 2007 Microchip Technology Inc. DS39605F-page 33
PIC18F1220/1320
4.0 RESET
The PIC18F1220/1320 devices differentiate between
various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR
Reset during normal operation
c) MCLR Reset during Sleep
d) Watchdog Timer (WDT) Reset (during
execution)
e) Programmable Brown-out Reset (BOR)
f) RESET Instruction
g) Stack Full Reset
h) Stack Underflow Reset
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state”, depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register
(Register 4-1), RI
, TO, PD, POR and BOR, are set or
cleared differently in different Reset situations, as
indicated in Table 4-2. These bits are used in software
to determine the nature of the Reset. See Table 4-3 for
a full description of the Reset states of all registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 4-1.
The Enhanced MCU devices have a MCLR
noise filter
in the MCLR
Reset path. The filter will detect and
ignore small pulses.
The MCLR
pin is not driven low by any internal Resets,
including the WDT.
The MCLR
input provided by the MCLR pin can be
disabled with the MCLRE bit in Configuration
Register 3H (CONFIG3H<7>).
FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
R
Q
External Reset
MCLR
VDD
OSC1
WDT
Time-out
V
DD Rise
Detect
OST/PWRT
INTRC
(1)
POR Pulse
OST
10-bit Ripple Counter
PWRT
Chip_Reset
11-bit Ripple Counter
Enable OST
(2)
Enable PWRT
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
2: See Table 4-1 for time-out situations.
Brown-out
Reset
BOR
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
Sleep
( )_IDLE
1024 Cycles
65.5 ms
32 μs
MCLRE