Datasheet
Table Of Contents
- Low-Power Features:
- Oscillators:
- Peripheral Highlights:
- Special Microcontroller Features:
- Pin Diagrams
- Table of Contents
- Most Current Data Sheet
- Errata
- Customer Notification System
- 1.0 Device Overview
- 2.0 Oscillator Configurations
- 3.0 Power Managed Modes
- 4.0 Reset
- FIGURE 4-1: Simplified Block Diagram of On-Chip Reset Circuit
- 4.1 Power-on Reset (POR)
- 4.2 Power-up Timer (PWRT)
- 4.3 Oscillator Start-up Timer (OST)
- 4.4 PLL Lock Time-out
- 4.5 Brown-out Reset (BOR)
- 4.6 Time-out Sequence
- TABLE 4-1: Time-out in Various Situations
- Register 4-1: RCON Register Bits and Positions
- TABLE 4-2: Status Bits, Their Significance and the Initialization Condition for RCON Register
- TABLE 4-3: Initialization Conditions for All Registers
- FIGURE 4-3: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise < Tpwrt)
- FIGURE 4-4: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 1
- FIGURE 4-5: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 2
- FIGURE 4-6: Slow Rise Time (MCLR Tied to Vdd, Vdd Rise > Tpwrt)
- FIGURE 4-7: Time-out Sequence on POR W/PLL Enabled (MCLR Tied to Vdd)
- 5.0 Memory Organization
- FIGURE 5-1: Program Memory Map and Stack for PIC18F1220
- 5.1 Program Memory Organization
- 5.2 Return Address Stack
- 5.3 Fast Register Stack
- 5.4 PCL, PCLATH and PCLATU
- 5.5 Clocking Scheme/Instruction Cycle
- 5.6 Instruction Flow/Pipelining
- 5.7 Instructions in Program Memory
- 5.8 Look-up Tables
- 5.9 Data Memory Organization
- 5.10 Access Bank
- 5.11 Bank Select Register (BSR)
- 5.12 Indirect Addressing, INDF and FSR Registers
- 5.13 Status Register
- 5.14 RCON Register
- 6.0 Flash Program Memory
- 7.0 Data EEPROM Memory
- 8.0 8 X 8 Hardware Multiplier
- 9.0 Interrupts
- 10.0 I/O Ports
- FIGURE 10-1: Generic I/O Port Operation
- 10.1 PORTA, TRISA and LATA Registers
- EXAMPLE 10-1: Initializing PORTA
- FIGURE 10-2: Block Diagram of RA3:RA0 Pins
- FIGURE 10-3: Block Diagram of OSC2/CLKO/RA6 Pin
- FIGURE 10-4: Block Diagram of RA4/T0CKI Pin
- FIGURE 10-5: Block Diagram of OSC1/CLKI/RA7 Pin
- FIGURE 10-6: MCLR/Vpp/RA5 Pin Block Diagram
- TABLE 10-1: PORTA Functions
- TABLE 10-2: Summary of Registers Associated with PORTA
- 10.2 PORTB, TRISB and LATB Registers
- EXAMPLE 10-2: Initializing PORTB
- FIGURE 10-7: Block Diagram of RB0/AN4/INT0 Pin
- FIGURE 10-8: Block Diagram of RB1/AN5/TX/CK/INT1 Pin
- FIGURE 10-9: Block Diagram of RB2/P1B/INT2 Pin
- FIGURE 10-10: Block Diagram of RB3/CCP1/P1A Pin
- FIGURE 10-11: Block Diagram of RB4/AN6/RX/DT/KBI0 Pin
- FIGURE 10-12: Block Diagram of RB5/PGM/KBI1 Pin
- FIGURE 10-13: Block Diagram of RB6/PGC/T1OSO/T13CKI/P1C/KBI2 Pin
- FIGURE 10-14: Block Diagram of RB7/PGD/T1OSI/P1D/KBI3 Pin
- TABLE 10-3: PORTB Functions
- TABLE 10-4: Summary of Registers Associated with PORTB
- 11.0 Timer0 Module
- 12.0 Timer1 Module
- 13.0 Timer2 Module
- 14.0 Timer3 Module
- 15.0 Enhanced Capture/ Compare/PWM (ECCP) Module
- Register 15-1: CCP1CON Register for Enhanced CCP Operation
- 15.1 ECCP Outputs
- 15.2 CCP Module
- 15.3 Capture Mode
- 15.4 Compare Mode
- 15.5 Enhanced PWM Mode
- 15.5.1 PWM Period
- 15.5.2 PWM Duty Cycle
- 15.5.3 PWM Output Configurations
- 15.5.4 Half-Bridge Mode
- 15.5.5 Full-Bridge Mode
- 15.5.6 Programmable Dead-Band Delay
- 15.5.7 Enhanced PWM Auto-Shutdown
- 15.5.8 Start-up Considerations
- 15.5.9 Setup for PWM Operation
- 15.5.10 Operation in Low-Power Modes
- 15.5.11 Effects of a Reset
- 16.0 Enhanced Addressable Universal Synchronous Asynchronous Receiver Transmitter (EUSART)
- 16.1 Asynchronous Operation in Power Managed Modes
- 16.2 EUSART Baud Rate Generator (BRG)
- 16.3 EUSART Asynchronous Mode
- 16.4 EUSART Synchronous Master Mode
- 16.5 EUSART Synchronous Slave Mode
- 17.0 10-Bit Analog-to-Digital Converter (A/D) Module
- Register 17-1: ADCON0: A/D Control Register 0
- Register 17-2: ADCON1: A/D Control Register 1
- Register 17-3: ADCON2: A/D Control Register 2
- FIGURE 17-1: A/D Block Diagram
- FIGURE 17-2: Analog Input Model
- 17.1 A/D Acquisition Requirements
- 17.2 A/D Vref+ and Vref- References
- 17.3 Selecting and Configuring Automatic Acquisition Time
- 17.4 Selecting the A/D Conversion Clock
- 17.5 Operation in Low-Power Modes
- 17.6 Configuring Analog Port Pins
- 17.7 A/D Conversions
- 17.8 Use of the CCP1 Trigger
- 18.0 Low-Voltage Detect
- 19.0 Special Features of the CPU
- 19.1 Configuration Bits
- TABLE 19-1: Configuration Bits and Device IDs
- Register 19-1: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)
- Register 19-2: CONFIG2L: Configuration Register 2 Low (Byte Address 300002h)
- Register 19-3: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)
- Register 19-4: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)
- Register 19-5: CONFIG4L: Configuration Register 4 Low (Byte Address 300006h)
- Register 19-6: CONFIG5L: Configuration Register 5 Low (Byte Address 300008h)
- Register 19-7: CONFIG5H: Configuration Register 5 High (Byte Address 300009h)
- Register 19-8: CONFIG6L: Configuration Register 6 Low (Byte Address 30000Ah)
- Register 19-9: CONFIG6H: Configuration Register 6 High (Byte Address 30000Bh)
- Register 19-10: CONFIG7L: Configuration Register 7 Low (Byte Address 30000Ch)
- Register 19-11: CONFIG7H: Configuration Register 7 High (Byte Address 30000Dh)
- Register 19-12: DEVID1: Device ID Register 1 for PIC18F1220/1320 Devices
- Register 19-13: DEVID2: Device ID Register 2 for PIC18F1220/1320 Devices
- 19.2 Watchdog Timer (WDT)
- 19.3 Two-Speed Start-up
- 19.4 Fail-Safe Clock Monitor
- 19.5 Program Verification and Code Protection
- 19.6 ID Locations
- 19.7 In-Circuit Serial Programming
- 19.8 In-Circuit Debugger
- 19.9 Low-Voltage ICSP Programming
- 19.1 Configuration Bits
- 20.0 Instruction Set Summary
- 21.0 Development Support
- 21.1 MPLAB Integrated Development Environment Software
- 21.2 MPASM Assembler
- 21.3 MPLAB C18 and MPLAB C30 C Compilers
- 21.4 MPLINK Object Linker/ MPLIB Object Librarian
- 21.5 MPLAB ASM30 Assembler, Linker and Librarian
- 21.6 MPLAB SIM Software Simulator
- 21.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator
- 21.8 MPLAB REAL ICE In-Circuit Emulator System
- 21.9 MPLAB ICD 2 In-Circuit Debugger
- 21.10 MPLAB PM3 Device Programmer
- 21.11 PICSTART Plus Development Programmer
- 21.12 PICkit 2 Development Programmer
- 21.13 Demonstration, Development and Evaluation Boards
- 22.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
- 22.1 DC Characteristics: Supply Voltage PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial)
- 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1...
- 22.3 DC Characteristics: PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial)
- 22.4 AC (Timing) Characteristics
- 22.4.1 Timing Parameter Symbology
- 22.4.2 Timing Conditions
- 22.4.3 Timing Diagrams and Specifications
- FIGURE 22-6: External Clock Timing (All Modes Except PLL)
- TABLE 22-4: External Clock Timing Requirements
- TABLE 22-5: PLL Clock Timing Specifications, HS/HSPLL Mode (Vdd = 4.2V to 5.5V)
- TABLE 22-6: Internal RC Accuracy: PIC18F1220/1320 (INDUSTRIAL) PIC18LF1220/1320 (INDUSTRIAL)
- FIGURE 22-7: CLKO and I/O Timing
- TABLE 22-7: CLKO and I/O Timing Requirements
- FIGURE 22-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing
- FIGURE 22-9: Brown-out Reset Timing
- TABLE 22-8: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset ...
- FIGURE 22-10: Timer0 and Timer1 External Clock Timings
- TABLE 22-9: Timer0 and Timer1 External Clock Requirements
- FIGURE 22-11: Capture/Compare/PWM Timings (All CCP Modules)
- TABLE 22-10: Capture/Compare/PWM Requirements (All CCP Modules)
- FIGURE 22-12: EUSART Synchronous Transmission (Master/Slave) Timing
- TABLE 22-11: EUSART Synchronous Transmission Requirements
- FIGURE 22-13: EUSART Synchronous Receive (Master/Slave) Timing
- TABLE 22-12: EUSART Synchronous Receive Requirements
- TABLE 22-13: A/D Converter Characteristics: PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Indust...
- FIGURE 22-14: A/D Conversion Timing
- TABLE 22-14: A/D Conversion Requirements
- 23.0 DC and AC Characteristics Graphs and Tables
- FIGURE 23-1: Typical Idd vs. Fosc Over Vdd PRI_RUN, EC Mode, +25˚C
- FIGURE 23-2: Maximum Idd vs. Fosc Over Vdd PRI_RUN, EC Mode, -40˚C to +85˚C
- FIGURE 23-3: Maximum Idd vs. Fosc Over Vdd PRI_RUN, EC Mode, -40˚C to +125˚C
- FIGURE 23-4: Typical Idd vs. Fosc Over Vdd PRI_RUN, EC Mode, +25˚C
- FIGURE 23-5: Maximum Idd vs. Fosc Over Vdd PRI_RUN, EC Mode, -40˚C to +125˚C
- FIGURE 23-6: Typical Idd vs. Fosc Over Vdd PRI_RUN, EC Mode, +25˚C
- FIGURE 23-7: Maximum Idd vs. Fosc Over Vdd PRI_RUN, EC Mode, -40˚C to +125˚C
- FIGURE 23-8: Typical Idd vs. Fosc Over Vdd PRI_IDLE, EC Mode, +25˚C
- FIGURE 23-9: Maximum Idd vs. Fosc Over Vdd PRI_IDLE, EC Mode, -40˚C to +85˚C
- FIGURE 23-10: Maximum Idd vs. Fosc Over Vdd PRI_IDLE, EC Mode, -40˚C to +125˚C
- FIGURE 23-11: Typical Idd vs. Fosc Over Vdd PRI_IDLE, EC Mode, +25˚C
- FIGURE 23-12: Maximum Idd vs. Fosc Over Vdd PRI_IDLE, EC Mode, -40˚C to +125˚C
- FIGURE 23-13: Typical Idd vs. Fosc Over Vdd PRI_IDLE, EC Mode, +25˚C
- FIGURE 23-14: Maximum Idd vs. Fosc Over Vdd PRI_IDLE, EC Mode, -40˚C to +125˚C
- FIGURE 23-15: Typical Ipd vs. Vdd (+25˚C), 125 kHz to 8 MHz RC_RUN Mode, All Peripherals Disabled
- FIGURE 23-16: Maximum Ipd vs. Vdd (-40˚C to +125˚C), 125 kHz to 8 MHz RC_RUN Mode, All Peripheral...
- FIGURE 23-17: Typical and Maximum Ipd vs. Vdd (-40˚C to +125˚C), 31.25 kHz RC_RUN Mode, All Perip...
- FIGURE 23-18: Typical Ipd vs. Vdd (+25˚C), 125 kHz to 8 MHz RC_IDLE Mode, All Peripherals Disabled
- FIGURE 23-19: Maximum Ipd vs. Vdd (-40˚C to +125˚C), 125 kHz to 8 MHz RC_IDLE Mode, All Periphera...
- FIGURE 23-20: Typical and Maximum Ipd vs. Vdd (-40˚C to +125˚C), 31.25 kHz RC_IDLE Mode, All Peri...
- FIGURE 23-21: Ipd SEC_RUN Mode, -10˚C to +70˚C, 32.768 kHz XTAL, 2 x 22 pF, All Peripherals Disabled
- FIGURE 23-22: Ipd SEC_IDLE Mode, -10˚C to +70˚C, 32.768 kHz, 2 x 22 pF, All Peripherals Disabled
- FIGURE 23-23: Total Ipd, -40˚C to +125˚C Sleep Mode, All Peripherals Disabled
- FIGURE 23-24: Voh vs. Ioh Over Temperature (-40˚C to +125˚C), Vdd = 3.0V
- FIGURE 23-25: Voh vs. Ioh Over Temperature (-40˚C to +125˚C), Vdd = 5.0V
- FIGURE 23-26: Vol vs. Iol Over Temperature (-40˚C to +125˚C), Vdd = 3.0V
- FIGURE 23-27: Vol vs. Iol Over Temperature (-40˚C to +125˚C), Vdd = 5.0V
- FIGURE 23-28: DIpd Timer1 Oscillator, -10˚C to +70˚C Sleep Mode, TMR1 Counter Disabled
- FIGURE 23-29: DIpd FSCM vs. Vdd Over Temperature PRI_IDLE Mode, EC Oscillator at 32 kHz, -40˚C to...
- FIGURE 23-30: DIpd WDT, -40˚C to +125˚C Sleep Mode, All Peripherals Disabled
- FIGURE 23-31: DIpd LVD vs. Vdd Sleep Mode, LVDL3:LVDL0 = 0001 (2V)
- FIGURE 23-32: DIpd BOR vs. Vdd, -40˚C to +125˚C Sleep Mode, BORV1:BORV0 = 11 (2V)
- FIGURE 23-33: DIpd A/D, -40˚C to +125˚C Sleep Mode, A/D Enabled (Not Converting)
- FIGURE 23-34: Average Fosc vs. Vdd for Various R’s External RC Mode, C = 20 pF, Temperature = +25˚C
- FIGURE 23-35: Average Fosc vs. Vdd for Various R’s External RC Mode, C = 100 pF, Temperature = +25˚C
- FIGURE 23-36: Average Fosc vs. Vdd for Various R’s External RC Mode, C = 300 pF, Temperature = +25˚C
- 24.0 Packaging Information
- Appendix A: Revision History
- Appendix B: Device Differences
- Appendix C: Conversion Considerations
- Appendix D: Migration from Baseline to Enhanced Devices
- Appendix E: Migration from Mid-Range to Enhanced Devices
- Appendix F: Migration from High-End to Enhanced Devices
- INDEX
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Reader Response
- PIC18F1220/1320 Product Identification System
- Worldwide Sales and Service
© 2007 Microchip Technology Inc. DS39605F-page 185
PIC18F1220/1320
19.5 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other PIC
devices.
The user program memory is divided into three blocks.
One of these is a boot block of 512 bytes. The remain-
der of the memory is divided into two blocks on binary
boundaries.
Each of the three blocks has three protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 19-5 shows the program memory organization
for 4 and 8-Kbyte devices and the specific code protec-
tion bit associated with each block. The actual locations
of the bits are summarized in Table 19-3.
FIGURE 19-5: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F1220/1320
TABLE 19-3: SUMMARY OF CODE PROTECTION REGISTERS
Block Code
Protection
Controlled By:
MEMORY SIZE/DEVICE
Block Code
Protection
Controlled By:
Address
Range
4Kbytes
(PIC18F1220)
8Kbytes
(PIC18F1320)
Address
Range
CPB, WRTB, EBTRB
000000h
0001FFh
Boot Block Boot Block
000000h
0001FFh
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
000200h
0007FFh
Block 0
Block 0
000200h
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
000800h
000FFFh
Block 1
000FFFh
(Unimplemented
Memory Space)
001000h
Unimplemented
Read ‘0’s
Block 1
001000h
CP1, WRT1, EBTR1
001FFFh
1FFFFFh
Unimplemented
Read ‘0’s
002000h
1FFFFFh
(Unimplemented
Memory Space)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
300008h CONFIG5L
— — — — — —CP1CP0
300009h CONFIG5H CPD CPB
— — — — — —
30000Ah CONFIG6L
— — — — — — WRT1 WRT0
30000Bh CONFIG6H WRTD WRTB WRTC
— — — — —
30000Ch CONFIG7L — — — — — — EBTR1 EBTR0
30000Dh CONFIG7H
— EBTRB — — — — — —
Legend: Shaded cells are unimplemented.