Datasheet

© 2007 Microchip Technology Inc. DS39605F-page 181
PIC18F1220/1320
TABLE 19-2: SUMMARY OF WATCHDOG TIMER REGISTERS
19.3 Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the
latency period from oscillator start-up to code execution
by allowing the microcontroller to use the INTRC oscil-
lator as a clock source until the primary clock source is
available. It is enabled by setting the IESO bit in
Configuration Register 1H (CONFIG1H<7>).
Two-Speed Start-up is available only if the primary oscil-
lator mode is LP, XT, HS or HSPLL (crystal-based
modes). Other sources do not require an OST start-up
delay; for these, Two-Speed Start-up is disabled.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the
internal oscillator block as the clock source, following
the time-out of the Power-up Timer after a Power-on
Reset is enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
Because the OSCCON register is cleared on Reset
events, the INTOSC (or postscaler) clock source is not
initially available after a Reset event; the INTRC clock
is used directly at its base frequency. To use a higher
clock speed on wake-up, the INTOSC or postscaler
clock sources can be selected to provide a higher clock
speed by setting bits, IFRC2:IFRC0, immediately after
Reset. For wake-ups from Sleep, the INTOSC or
postscaler clock sources can be selected by setting
IFRC2:IFRC0 prior to entering Sleep mode.
In all other power managed modes, Two-Speed Start-up
is not used. The device will be clocked by the currently
selected clock source until the primary clock source
becomes available. The setting of the IESO bit is
ignored.
19.3.1 SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
While using the INTRC oscillator in Two-Speed Start-
up, the device still obeys the normal command
sequences for entering power managed modes, includ-
ing serial SLEEP instructions (refer to Section 3.1.3
“Multiple Sleep Commands”). In practice, this means
that user code can change the SCS1:SCS0 bit settings
and issue SLEEP commands before the OST times out.
This would allow an application to briefly wake-up, per-
form routine “housekeeping” tasks and return to Sleep
before the device starts to operate from the primary
oscillator.
User code can also check if the primary clock source is
currently providing the system clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the system clock.
Otherwise, the internal oscillator block is providing the
clock during wake-up from Reset or Sleep mode.
FIGURE 19-2: TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL)
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CONFIG2H
— — — WDTPS3 WDTPS2 WDTPS2 WDTPS0 WDTEN
RCON
IPEN — — RI TO PD POR BOR
WDTCON — — — — — — —SWDTEN
Legend: Shaded cells are not used by the Watchdog Timer.
Q1
Q3 Q4
OSC1
Peripheral
Program
PC PC + 2
INTOSC
PLL Clock
Q1
PC + 6
Q2
Output
Q3
Q4
Q1
CPU Clock
PC + 4
Clock
Counter
Q2
Q2
Q3 Q4
Note 1: T
OST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
Wake from Interrupt Event
TPLL
(1)
12345678
Clock Transition
OSTS bit Set
Multiplexer
TOST
(1)