Datasheet

PIC18F1220/1320
DS39605F-page 116 © 2007 Microchip Technology Inc.
15.1 ECCP Outputs
The Enhanced CCP module may have up to four
outputs, depending on the selected operating mode.
These outputs, designated P1A through P1D, are
multiplexed with I/O pins on PORTB. The pin
assignments are summarized in Table 15-1.
To configure I/O pins as PWM outputs, the proper PWM
mode must be selected by setting the P1Mn and
CCP1Mn bits (CCP1CON<7:6> and <3:0>,
respectively). The appropriate TRISB direction bits for
the port pins must also be set as outputs.
TABLE 15-1: PIN ASSIGNMENTS FOR VARIOUS ECCP MODES
15.2 CCP Module
Capture/Compare/PWM Register 1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
TABLE 15-2: CCP MODE – TIMER
RESOURCE
15.3 Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the 16-bit
value of the TMR1 or TMR3 registers when an event
occurs on pin RB3/CCP1/P1A. An event is defined as
one of the following:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
The event is selected by control bits, CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit, CCP1IF (PIR1<2>), is set; it must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value is overwritten by the new captured value.
15.3.1 CCP PIN CONFIGURATION
In Capture mode, the RB3/CCP1/P1A pin should be
configured as an input by setting the TRISB<3> bit.
15.3.2 TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the capture feature
(either Timer1 and/or Timer3) must be running in Timer
mode or Synchronized Counter mode. In Asynchro-
nous Counter mode, the capture operation may not
work. The timer to be used with the CCP module is
selected in the T3CON register.
15.3.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit,
CCP1IE (PIE1<2>), clear while changing capture
modes to avoid false interrupts and should clear the
flag bit, CCP1IF, following any such change in
operating mode.
ECCP Mode
CCP1CON
Configuration
RB3 RB2 RB6 RB7
Compatible CCP 00xx 11xx CCP1
RB2/INT2 RB6/PGC/T1OSO/T13CKI/KBI2 RB7/PGD/T1OSI/KBI3
Dual PWM 10xx 11xx P1A P1B
RB6/PGC/T1OSO/T13CKI/KBI2 RB7/PGD/T1OSI/KBI3
Quad PWM x1xx 11xx P1A P1B P1C P1D
Legend: x = Don’t care. Shaded cells indicate pin assignments not used by ECCP in a given mode.
Note 1: TRIS register values must be configured appropriately.
CCP Mode Timer Resource
Capture
Compare
PWM
Timer1 or Timer3
Timer1 or Timer3
Timer2
Note: If the RB3/CCP1/P1A is configured as an
output, a write to the port can cause a
capture condition.