PIC18F1220/1320 Data Sheet 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology © 2007 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC18F1220/1320 18/20/28-Pin High-Performance, Enhanced Flash MCUs with 10-bit A/D and nanoWatt Technology Low-Power Features: Peripheral Highlights: • Power Managed modes: - Run: CPU on, peripherals on - Idle: CPU off, peripherals on - Sleep: CPU off, peripherals off • Power Consumption modes: - PRI_RUN: 150 μA, 1 MHz, 2V - PRI_IDLE: 37 μA, 1 MHz, 2V - SEC_RUN: 14 μA, 32 kHz, 2V - SEC_IDLE: 5.8 μA, 32 kHz, 2V - RC_RUN: 110 μA, 1 MHz, 2V - RC_IDLE: 52 μA, 1 MHz, 2V - Sleep: 0.
PIC18F1220/1320 Pin Diagrams 20-Pin SSOP 18-Pin PDIP, SOIC 16 OSC1/CLKI/RA7 15 OSC2/CLKO/RA6 14 VDD/AVDD 3 18 OSC1/CLKI/RA7 MCLR/VPP/RA5 4 17 OSC2/CLKO/RA6 16 VDD 15 AVDD VSS 5 RB7/PGD/T1OSI/ P1D/KBI3 RB6/PGC/T1OSO/ T13CKI/P1C/KBI2 AVSS 6 RA2/AN2/VREF- 7 RA3/AN3/VREF+ 8 13 RB0/AN4/INT0 9 12 RB5/PGM/KBI1 10 11 RB4/AN6/RX/ DT/KBI0 RA2/AN2/VREF- 6 RA3/AN3/VREF+ 7 12 RB0/AN4/INT0 8 11 RB5/PGM/KBI1 RB1/AN5/TX/ CK/INT1 9 10 RB4/AN6/RX/ DT/KBI0 RA1/AN1/LVDIN RA0/AN
PIC18F1220/1320 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Oscillator Configurations ............................................................................................................................................................ 11 3.0 Power Managed Modes .......................................................................
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PIC18F1220/1320 1.0 DEVICE OVERVIEW This document contains device specific information for the following devices: • PIC18F1220 • PIC18F1320 This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price – with the addition of high endurance Enhanced Flash program memory.
PIC18F1220/1320 1.3 Details on Individual Family Members A block diagram of the PIC18F1220/1320 device architecture is provided in Figure 1-1. The pinouts for this device family are listed in Table 1-2. Devices in the PIC18F1220/1320 family are available in 18-pin, 20-pin and 28-pin packages. A block diagram for this device family is shown in Figure 1-1.
PIC18F1220/1320 FIGURE 1-1: PIC18F1220/1320 BLOCK DIAGRAM Data Bus<8> 21 Table Pointer <2> 21 8 8 8 PORTA Data Latch 8 RA0/AN0 Data RAM inc/dec logic RA1/AN1/LVDIN 21 Address Latch 20 Address Latch Program Memory (4 Kbytes) PIC18F1220 (8 Kbytes) PIC18F1320 RA2/AN2/VREF- PCLATU PCLATH PCU PCH PCL Program Counter 12(2) Address<12> 4 BSR 31 Level Stack Data Latch 16 Decode Table Latch RA3/AN3/VREF+ 12 4 FSR0 Bank0, F FSR1 FSR2 12 RA4/T0CKI MCLR/VPP/RA5(1) OSC2/CLKO/RA6(2) inc/dec logic
PIC18F1220/1320 TABLE 1-2: PIC18F1220/1320 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PDIP/ SSOP SOIC MCLR/VPP/RA5 MCLR 4 4 QFN 16 18 Buffer Type I ST P I — ST 1 VPP RA5 OSC1/CLKI/RA7 OSC1 Pin Type 21 I CLKI I RA7 I/O OSC2/CLKO/RA6 OSC2 15 17 Description Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Oscillator crystal or external clock input.
PIC18F1220/1320 TABLE 1-2: PIC18F1220/1320 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP/ SSOP SOIC QFN Pin Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
PIC18F1220/1320 NOTES: DS39605F-page 10 © 2007 Microchip Technology Inc.
PIC18F1220/1320 2.0 OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types The PIC18F1220 and PIC18F1320 devices can be operated in ten different oscillator modes. The user can program the configuration bits, FOSC3:FOSC0, in Configuration Register 1H to select one of these ten modes: 1. 2. 3. 4. LP XT HS HSPLL 5. RC 6. RCIO 7. INTIO1 8. INTIO2 9. EC 10. ECIO 2.
PIC18F1220/1320 Osc Type LP XT HS CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq Typical Capacitor Values Tested: C1 C2 32 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF 1 MHz 33 pF 33 pF 4 MHz 27 pF 27 pF 4 MHz 27 pF 27 pF 8 MHz 22 pF 22 pF 20 MHz 15 pF 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized.
PIC18F1220/1320 2.4 External Clock Input The EC and ECIO Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset, or after an exit from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes, or to synchronize other logic. Figure 2-4 shows the pin connections for the EC Oscillator mode.
PIC18F1220/1320 2.6 Internal Oscillator Block The PIC18F1220/1320 devices include an internal oscillator block, which generates two different clock signals; either can be used as the system’s clock source. This can eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC) is an 8 MHz clock source, which can be used to directly drive the system clock. It also drives a postscaler, which can provide a range of clock frequencies from 125 kHz to 4 MHz.
PIC18F1220/1320 REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: Frequency Tuning bits 011111 = Maximum frequency • • • • 000001 000000 = Center frequency. Oscillator module is running at the calibrated frequency. 111111 • • • • 100000 = Minimum frequency Legend: R = Readable bit -n = Value at POR 2.
PIC18F1220/1320 2.7.1 OSCILLATOR CONTROL REGISTER when the internal oscillator block has stabilized and is providing the system clock in RC Clock modes or during Two-Speed Start-ups. The T1RUN bit (T1CON<6>) indicates when the Timer1 oscillator is providing the system clock in Secondary Clock modes. In power managed modes, only one of these three bits will be set at any time.
PIC18F1220/1320 REGISTER 2-2: OSCCON REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0 IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 bit 7 bit 0 bit 7 IDLEN: Idle Enable bits 1 = Idle mode enabled; CPU core is not clocked in power managed modes 0 = Run mode enabled; CPU core is clocked in Run modes, but not Sleep mode bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits 111 = 8 MHz (8 MHz source drives clock directly) 110 = 4 MHz 101 = 2 MHz 100 = 1 MHz 011 = 500 kHz 010 =
PIC18F1220/1320 2.7.2 OSCILLATOR TRANSITIONS The PIC18F1220/1320 devices contain circuitry to prevent clocking “glitches” when switching between clock sources. A short pause in the system clock occurs during the clock switch. The length of this pause is between 8 and 9 clock periods of the new clock source. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources.
PIC18F1220/1320 3.0 POWER MANAGED MODES For PIC18F1220/1320 devices, the power managed modes are invoked by using the existing SLEEP instruction. All modes exit to PRI_RUN mode when triggered by an interrupt, a Reset or a WDT time-out (PRI_RUN mode is the normal full power execution mode; the CPU and peripherals are clocked by the primary oscillator source). In addition, power managed Run modes may also exit to Sleep mode, or their corresponding Idle mode.
PIC18F1220/1320 3.1.2 ENTERING POWER MANAGED MODES In general, entry, exit and switching between power managed clock sources requires clock source switching. In each case, the sequence of events is the same. Any change in the power managed mode begins with loading the OSCCON register and executing a SLEEP instruction.
PIC18F1220/1320 TABLE 3-2: Power Managed Mode COMPARISON BETWEEN POWER MANAGED MODES CPU is Clocked by ... WDT Time-out causes a ... Peripherals are Clocked by ...
PIC18F1220/1320 FIGURE 3-1: TIMING TRANSITION FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC FIGURE 3-2: PC + 2 TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(1) PLL Clock Output TPLL(1) CPU Clock Peripheral Clock Program Counter PC Wake Event Note 1: PC + 2 PC + 4 PC + 6 PC + 8 OSTS bit Set TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
PIC18F1220/1320 3.3.1 PRI_IDLE MODE This mode is unique among the three Low-Power Idle modes, in that it does not disable the primary system clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “warm up” or transition from another oscillator. When a wake event occurs, the CPU is clocked from the primary clock source.
PIC18F1220/1320 3.3.2 SEC_IDLE MODE When a wake event occurs, the peripherals continue to be clocked from the Timer1 oscillator. After a 10 μs delay following the wake event, the CPU begins executing code, being clocked by the Timer1 oscillator. The microcontroller operates in SEC_RUN mode until the primary clock becomes ready. When the primary clock becomes ready, a clock switchback to the primary clock occurs (see Figure 3-6).
PIC18F1220/1320 3.3.3 RC_IDLE MODE instruction was executed and the INTOSC source was already stable, the IOFS bit will remain set. If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. In RC_IDLE mode, the CPU is disabled, but the peripherals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode allows for controllable power conservation during Idle periods.
PIC18F1220/1320 3.4 Run Modes SEC_RUN mode is entered by clearing the IDLEN bit, setting SCS1:SCS0 = 01 and executing a SLEEP instruction. The system clock source is switched to the Timer1 oscillator (see Figure 3-9), the primary oscillator is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared. If the IDLEN bit is clear when a SLEEP instruction is executed, the CPU and peripherals are both clocked from the source selected using the SCS1:SCS0 bits.
PIC18F1220/1320 3.4.3 RC_RUN MODE Note: In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer and the primary clock is shut down. When using the INTRC source, this mode provides the best power conservation of all the Run modes, while still executing code. It works well for user applications which are not highly timing sensitive, or do not require high-speed clocks at all times.
PIC18F1220/1320 3.4.4 EXIT TO IDLE MODE An exit from a power managed Run mode to its corresponding Idle mode is executed by setting the IDLEN bit and executing a SLEEP instruction. The CPU is halted at the beginning of the instruction following the SLEEP instruction. There are no changes to any of the clock source status bits (OSTS, IOFS or T1RUN). While the CPU is halted, the peripherals continue to be clocked from the previously selected clock source. 3.4.5 3.
PIC18F1220/1320 TABLE 3-3: Clock in Power Managed Mode ACTIVITY AND EXIT DELAY ON WAKE FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Primary System Clock LP, XT, HS Primary System HSPLL Clock (1) (PRI_IDLE mode) EC, RC, INTRC (2) INTOSC T1OSC or INTRC(1) 5-10 μs(5) — OST EC, RC, INTRC(1) 5-10 μs(5) — 1 ms(4) IOFS (2) OSTS LP, XT, HS OST HSPLL OST + 2 ms EC, RC, INTRC(1) 5-10 μs(5) — None IOFS (2) Activity during Wake-up from Power Managed Mode Exit by Interrupt CPU and peripher
PIC18F1220/1320 3.5.2 EXIT BY RESET Normally, the device is held in Reset by the Oscillator Start-up Timer (OST) until the primary clock (defined in Configuration Register 1H) becomes ready. At that time, the OSTS bit is set and the device begins executing code. Code execution can begin before the primary clock becomes ready. If either the Two-Speed Start-up (see Section 19.3 “Two-Speed Start-up”) or Fail-Safe Clock Monitor (see Section 19.
PIC18F1220/1320 3.6.1 EXAMPLE – EUSART An adjustment may be indicated when the EUSART begins to generate framing errors, or receives data with errors while in Asynchronous mode. Framing errors indicate that the system clock frequency is too high – try decrementing the value in the OSCTUNE register to reduce the system clock frequency. Errors in data may suggest that the system clock speed is too low – increment OSCTUNE. 3.6.
PIC18F1220/1320 NOTES: DS39605F-page 32 © 2007 Microchip Technology Inc.
PIC18F1220/1320 4.0 RESET The PIC18F1220/1320 devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during Sleep Watchdog Timer (WDT) Reset (during execution) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets.
PIC18F1220/1320 4.1 Power-on Reset (POR) A Power-on Reset pulse is generated on-chip when VDD rise is detected. To take advantage of the POR circuitry, just tie the MCLR pin through a resistor (1k to 10 kΩ) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (parameter D004). For a slow rise time, see Figure 4-2. When the device starts normal operation (i.e.
PIC18F1220/1320 TABLE 4-1: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) and Brown-out Oscillator Configuration PWRTEN = 1 Exit from Low-Power Mode 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) PWRTEN = 0 HSPLL 66 ms (1) + 1024 TOSC + 2 ms (2) HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC EC, ECIO 66 ms(1) 5-10 μs(3) 5-10 μs(3) RC, RCIO 66 ms(1) 5-10 μs(3) 5-10 μs(3) INTIO1, INTIO2 66 ms(1) 5-10 μs(3) 5-10 μs(3) Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
PIC18F1220/1320 TABLE 4-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt TOSU 1220 1320 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 1220 1320 0000 0000 0000 0000 uuuu uuuu(3) TOSL 1220 1320 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 1220 1320 00-0 0000 00-0 0000 uu-u uuuu(3) PCLATU 1220 1320 ---0 0000 ---0 0000 ---u uuuu PCLATH 1220 1320 000
PIC18F1220/1320 TABLE 4-3: Register BSR INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices 1220 1320 Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt ---- 0000 ---- 0000 ---- uuuu INDF2 1220 1320 N/A N/A N/A POSTINC2 1220 1320 N/A N/A N/A POSTDEC2 1220 1320 N/A N/A N/A PREINC2 1220 1320 N/A N/A N/A PLUSW2 1220 1320 N/A N/A N/A FSR2H 1220 1320 ---- 0000 ---- 0000 ---- uuuu FS
PIC18F1220/1320 TABLE 4-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt TMR3H 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu TMR3L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu T3CON 1220 1320 0-00 0000 u-uu uuuu u-uu uuuu SPBRGH 1220 1320 0000 0000 0000 0000 uuuu uuuu SPBRG 1220 1320 0000 0000 0000 0000 uuuu uuuu RCREG 1220 1320 00
PIC18F1220/1320 FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 FIGURE 4-4: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 4-5: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET © 2007 Microchip Technology
PIC18F1220/1320 FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 1V 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT OST TIME-OUT TOST TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL ≈ 2 ms max. First three stages of the PWRT timer. DS39605F-page 40 © 2007 Microchip Technology Inc.
PIC18F1220/1320 5.0 MEMORY ORGANIZATION There are three memory types in Enhanced MCU devices. These memory types are: • Program Memory • Data RAM • Data EEPROM Data and program memory use separate busses, which allows for concurrent access of these types. Additional detailed information for Flash program memory and data EEPROM is provided in Section 6.0 “Flash Program Memory” and Section 7.0 “Data EEPROM Memory”, respectively. 5.
PIC18F1220/1320 5.2 5.2.2 Return Address Stack The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL instruction is executed, or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions.
PIC18F1220/1320 REGISTER 5-1: STKPTR REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 bit 7(1) STKFUL: Stack Full Flag bit 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6(1) STKUNF: Stack Underflow Flag bit 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user so
PIC18F1220/1320 5.3 Fast Register Stack A “fast return” option is available for interrupts. A fast register stack is provided for the Status, WREG and BSR registers and is only one in depth. The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt. The values in the registers are then loaded back into the working registers, if the RETFIE, FAST instruction is used to return from the interrupt.
PIC18F1220/1320 5.5 Clocking Scheme/Instruction Cycle 5.6 Instruction Flow/Pipelining An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.
PIC18F1220/1320 5.7 Instructions in Program Memory The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). Figure 5-5 shows an example of how instruction words are stored in the program memory. To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read ‘0’ (see Section 5.
PIC18F1220/1320 5.8 Look-up Tables Look-up tables are implemented two ways: • Computed GOTO • Table Reads 5.8.1 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (see Example 5-4). A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW 0xnn instructions. WREG is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction.
PIC18F1220/1320 FIGURE 5-6: DATA MEMORY MAP FOR PIC18F1220/1320 DEVICES BSR<3:0> = 0000 Data Memory Map 00h Access RAM FFh GPR Bank 0 000h 07Fh 080h 0FFh Access Bank Access RAM Low = 0001 = 1110 Bank 1 to Bank 14 00h 7Fh Access RAM High 80h (SFRs) FFh Unused Read ‘00h’ When a = 0, The BSR is ignored and the Access Bank is used. = 1111 00h Unused FFh SFR Bank 15 EFFh F00h F7Fh F80h FFFh The first 128 bytes are General Purpose RAM (from Bank 0).
PIC18F1220/1320 5.9.2 SPECIAL FUNCTION REGISTERS The SFRs can be classified into two sets: those associated with the “core” function and those related to the peripheral functions. Those registers related to the “core” are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature.
PIC18F1220/1320 TABLE 5-2: File Name REGISTER FILE SUMMARY (PIC18F1220/1320) Bit 7 Bit 6 Bit 5 — — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Details on page: ---0 0000 36, 42 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 36, 42 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 36, 42 Return Stack Pointer 00-0 0000 36, 43 Holding Register for PC<20:16> TOSU STKPTR STKFUL STKUNF — PCLATU — — bit 21(3) Top-of-Stack Upper Byte (TOS<20:16>) Value on POR, BOR ---0 0000 36, 44 PCLAT
PIC18F1220/1320 TABLE 5-2: File Name REGISTER FILE SUMMARY (PIC18F1220/1320) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: TMR1H Timer1 Register High Byte xxxx xxxx 37, 108 TMR1L Timer1 Register Low Byte xxxx xxxx 37, 108 0000 0000 37, 103 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON TMR2 Timer2 Register 0000 0000 37, 109 PR2 Timer2 Period Register 1111 1111 37, 109 T2CON — TOUTPS3 TOUTPS2 ADRESH A/D
PIC18F1220/1320 5.10 Access Bank 5.11 The Access Bank is an architectural enhancement which is very useful for C compiler code optimization. The techniques used by the C compiler may also be useful for programs written in assembly. The need for a large general purpose memory space dictates a RAM banking scheme. The data memory is partitioned into as many as sixteen banks. When using direct addressing, the BSR should be configured for the desired bank.
PIC18F1220/1320 5.12 Indirect Addressing, INDF and FSR Registers Indirect addressing is a mode of addressing data memory, where the data memory address in the instruction is not fixed. An FSR register is used as a pointer to the data memory location that is to be read or written. Since this pointer is in RAM, the contents can be modified by the program. This can be useful for data tables in the data memory and for software stacks.
PIC18F1220/1320 FIGURE 5-8: INDIRECT ADDRESSING OPERATION RAM 0h Instruction Executed Opcode Address FFFh 12 File Address = Access of an Indirect Addressing Register BSR<3:0> Instruction Fetched 4 12 8 Opcode FIGURE 5-9: 12 File FSR INDIRECT ADDRESSING Indirect Addressing FSRnH:FSRnL 3 0 7 0 11 0 Location Select 0000h Data Memory(1) 0FFFh Note 1: For register file map detail, see Table 5-1. DS39605F-page 54 © 2007 Microchip Technology Inc.
PIC18F1220/1320 5.13 Status Register The Status register, shown in Register 5-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the Status register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the status is updated according to the instruction performed.
PIC18F1220/1320 5.14 RCON Register Note 1: If the BOR configuration bit is set (Brownout Reset enabled), the BOR bit is ‘1’ on a Power-on Reset. After a Brown-out Reset has occurred, the BOR bit will be cleared and must be set by firmware to indicate the occurrence of the next Brown-out Reset. The Reset Control (RCON) register contains flag bits that allow differentiation between the sources of a device Reset. These flags include the TO, PD, POR, BOR and RI bits. This register is readable and writable.
PIC18F1220/1320 6.0 FLASH PROGRAM MEMORY The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT). The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. Table read operations retrieve data from program memory and place it into TABLAT in the data RAM space.
PIC18F1220/1320 FIGURE 6-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. 6.
PIC18F1220/1320 REGISTER 6-1: EECON1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access program Flash memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EE or Configuration Select bit 1 = Access configuration registers 0 = Access program Flash or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase
PIC18F1220/1320 6.2.2 TABLAT – TABLE LATCH REGISTER 6.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The table latch is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the Table Pointer determine which byte is read from program or configuration memory into TABLAT.
PIC18F1220/1320 6.3 Reading the Flash Program Memory The TBLRD instruction is used to retrieve data from program memory and place it into data RAM. Table reads from program memory are performed one byte at a time. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT. TBLPTR points to a byte address in program space.
PIC18F1220/1320 6.4 6.4.1 Erasing Flash Program Memory The minimum erase block size is 32 words or 64 bytes under firmware control. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in Flash memory is not supported. FLASH PROGRAM MEMORY ERASE SEQUENCE The sequence of events for erasing a block of internal program memory location is: 1.
PIC18F1220/1320 6.5 Writing to Flash Program Memory The programming block size is 4 words or 8 bytes. Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 8 holding registers used by the table writes for programming. FIGURE 6-5: Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction must be executed 8 times for each programming operation.
PIC18F1220/1320 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'64 COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL TBLRD*+ MOVF MOVWF DECFSZ GOTO TABLAT, W POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; number of bytes in erase block ; point to
PIC18F1220/1320 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) WRITE_WORD_TO_HREGS MOVF POSTINC0, W MOVWF TABLAT TBLWT+* ; ; ; ; get low byte of buffer data and increment FSR0 present data to table latch short write to internal TBLWT holding register, increment TBLPTR ; loop until buffers are full DECFSZ COUNTER GOTO WRITE_WORD_TO_HREGS PROGRAM_MEMORY BCF INTCON, GIE MOVLW 55h MOVWF EECON2 MOVLW AAh MOVWF EECON2 BSF EECON1, WR NOP BSF INTCON, GIE DECFSZ COUNTER_HI GOTO PROGRAM_LOOP BCF EECON1
PIC18F1220/1320 NOTES: DS39605F-page 66 © 2007 Microchip Technology Inc.
PIC18F1220/1320 7.0 DATA EEPROM MEMORY The data EEPROM is readable and writable during normal operation over the entire VDD range. The data memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFR). There are four SFRs used to read and write the program and data EEPROM memory. These registers are: • • • • EECON1 EECON2 EEDATA EEADR The EEPROM data memory allows byte read and write.
PIC18F1220/1320 REGISTER 7-1: EECON1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access program Flash memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access configuration or calibration registers 0 = Access program Flash or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase E
PIC18F1220/1320 7.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation). 7.
PIC18F1220/1320 7.7 Operation During Code-Protect 7.8 Data EEPROM memory has its own code-protect bits in configuration words. External read and write operations are disabled if either of these mechanisms are enabled. Using the Data EEPROM The data EEPROM is a high endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often).
PIC18F1220/1320 8.0 8 x 8 HARDWARE MULTIPLIER Making the 8 x 8 multiplier execute in a single cycle gives the following advantages: 8.1 Introduction • Higher computational throughput • Reduces code size requirements for multiply algorithms An 8 x 8 hardware multiplier is included in the ALU of the PIC18F1220/1320 devices. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result.
PIC18F1220/1320 Example 8-3 shows the sequence to do a 16 x 16 unsigned multiply. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES3:RES0.
PIC18F1220/1320 9.0 INTERRUPTS The PIC18F1220/1320 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. High priority interrupt events will interrupt any low priority interrupts that may be in progress. There are ten registers which are used to control interrupt operation.
PIC18F1220/1320 FIGURE 9-1: INTERRUPT LOGIC TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE Wake-up if in Low-Power Mode Interrupt to CPU Vector to Location 0008h INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT0IF INT0IE GIEH/GIE ADIF ADIE ADIP IPEN IPEN RCIF RCIE RCIP GIEL/PEIE IPEN Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation INT0IF INT0IE ADIF ADIE ADIP RBIF RBIE RBIP RCIF RCIE RCIP INT0IF INT0IE Additional Peripheral Interrupts D
PIC18F1220/1320 9.1 INTCON Registers Note: The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits. REGISTER 9-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
PIC18F1220/1320 REGISTER 9-2: INTCON2 REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrup
PIC18F1220/1320 REGISTER 9-3: INTCON3 REGISTER R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt b
PIC18F1220/1320 9.2 PIR Registers Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Request (Flag) registers (PIR1, PIR2).
PIC18F1220/1320 REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 OSCFIF — — EEIF — LVDIF TMR3IF — bit 7 bit 0 bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = System clock operating bit 6-5 Unimplemented: Read as ‘0’ bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be clear
PIC18F1220/1320 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1, PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
PIC18F1220/1320 REGISTER 9-7: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 OSCFIE — — EEIE — LVDIE TMR3IE — bit 7 bit 0 bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6-5 Unimplemented: Read as ‘0’ bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 Unimplemented: Read as ‘0’ bit 2 LVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TM
PIC18F1220/1320 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1, IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
PIC18F1220/1320 REGISTER 9-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 U-0 U-0 R/W-1 U-0 R/W-1 R/W-1 U-0 OSCFIP — — EEIP — LVDIP TMR3IP — bit 7 bit 0 bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6-5 Unimplemented: Read as ‘0’ bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 Unimplemented: Read as ‘0’ bit 2 LVDIP: Low-Voltage Detect Interrupt Priority bit 1 = Hig
PIC18F1220/1320 9.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from a low-power mode. RCON also contains the bit that enables interrupt priorities (IPEN).
PIC18F1220/1320 9.6 INTn Pin Interrupts 9.7 External interrupts on the RB0/INT0, RB1/INT1 and RB2/INT2 pins are edge-triggered: either rising if the corresponding INTEDGx bit is set in the INTCON2 register, or falling if the INTEDGx bit is clear. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxE.
PIC18F1220/1320 NOTES: DS39605F-page 86 © 2007 Microchip Technology Inc.
PIC18F1220/1320 10.0 I/O PORTS Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation.
PIC18F1220/1320 FIGURE 10-2: BLOCK DIAGRAM OF RA3:RA0 PINS FIGURE 10-4: BLOCK DIAGRAM OF RA4/T0CKI PIN RD LATA RD LATA Data Bus D WR LATA or PORTA Q VDD CK Q P Data Bus D Q WR LATA or PORTA CK Q Data Latch D Q CK Q Data Latch N (1) I/O pin WR TRISA WR TRISA Analog Input Mode I/O pin(1) N VSS D Q CK Q VSS Schmitt Trigger Input Buffer TRIS Latch TRIS Latch RD TRISA RD TRISA Q Schmitt Trigger Input Buffer D Q D ENEN EN RD PORTA RD PORTA TMR0 Clock Input To A/D Conve
PIC18F1220/1320 FIGURE 10-6: MCLR/VPP/RA5 PIN BLOCK DIAGRAM MCLRE Data Bus MCLR/VPP/RA5 RD TRISA Schmitt Trigger RD LATA Latch Q D EN RD PORTA High-Voltage Detect HV Internal MCLR Filter Low-Level MCLR Detect TABLE 10-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit 0 ST Input/output port pin or analog input. RA1/AN1/LVDIN bit 1 ST Input/output port pin, analog input or Low-Voltage Detect input. RA2/AN2/VREF- bit 2 ST Input/output port pin, analog input or VREF-.
PIC18F1220/1320 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped.
PIC18F1220/1320 FIGURE 10-8: BLOCK DIAGRAM OF RB1/AN5/TX/CK/INT1 PIN EUSART Enable 1 TX/CK Data 0 TX/CK TRIS VDD RBPU(2) Analog Input Mode Data Bus WR LATB or PORTB WR TRISB Weak P Pull-up Data Latch D Q RB1 pin(1) CK TRIS Latch D Q CK TTL Input Buffer RD TRISB RD LATB Q D RD PORTB EN RD PORTB Schmitt Trigger Input Buffer INT1/CK Input Analog Input Mode To A/D Converter Note 1: 2: I/O pins have diode protection to VDD and VSS.
PIC18F1220/1320 FIGURE 10-9: BLOCK DIAGRAM OF RB2/P1B/INT2 PIN VDD RBPU(2) P Weak Pull-up P1B Enable P1B Data 1 P1B/D Tri-State Auto-Shutdown 0 Data Bus WR LATB or PORTB Data Latch D Q RB2 pin(1) CK TRIS Latch D Q WR TRISB TTL Input Buffer CK RD TRISB RD LATB Q D RD PORTB EN INT2 Input Note 1: 2: DS39605F-page 92 Schmitt Trigger RD PORTB I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
PIC18F1220/1320 FIGURE 10-10: BLOCK DIAGRAM OF RB3/CCP1/P1A PIN ECCP1(3) pin Output Enable ECCP1(4) pin Input Enable VDD RBPU(2) Weak P Pull-up P1A/C Tri-State Auto-Shutdown ECCP1/P1A Data Out VDD 1 P 0 RD LATB Data Bus WR LATB or PORTB D Q RB3 pin CK Q Data Latch D N Q VSS WR TRISB CK Q TTL Input Buffer TRIS Latch RD TRISB Q D EN RD PORTB ECCP1 Input Schmitt Trigger Note 1: I/O pins have diode protection to VDD and VSS.
PIC18F1220/1320 FIGURE 10-11: BLOCK DIAGRAM OF RB4/AN6/RX/DT/KBI0 PIN EUSART Enabled VDD RBPU(2) Analog Input Mode P Weak Pull-up DT TRIS DT Data 1 0 RD LATB Data Bus WR LATB or PORTB D Q RB4 pin CK Q Data Latch D WR TRISB CK Q Q TRIS Latch TTL Input Buffer RD TRISB Q Set RBIF EN RD PORTB From other RB7:RB4 pins D Q D RD PORTB EN RX/DT Input To A/D Converter Note 1: 2: Q1 Q3 Schmitt Trigger Analog Input Mode I/O pins have diode protection to VDD and VSS.
PIC18F1220/1320 FIGURE 10-12: BLOCK DIAGRAM OF RB5/PGM/KBI1 PIN VDD RBPU(2) Weak P Pull-up Data Latch Data Bus D WR LATB or PORTB Q I/O pin(1) CK TRIS Latch D Q WR TRISB TTL Input Buffer CK ST Buffer RD TRISB RD LATB Latch Q D RD PORTB EN Set RBIF Q Q1 D RD PORTB From other RB7:RB5 and RB4 pins EN Q3 RB7:RB5 in Serial Programming Mode Note 1: 2: I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
PIC18F1220/1320 FIGURE 10-13: BLOCK DIAGRAM OF RB6/PGC/T1OSO/T13CKI/P1C/KBI2 PIN ECCP1 P1C/D Enable VDD RBPU(2) P Weak Pull-up P1B/D Tri-State Auto-Shutdown P1C Data 1 0 RD LATB Data Bus WR LATB or PORTB D CK Q RB6 pin Q Data Latch D WR TRISB CK Q Q Timer1 Oscillator TRIS Latch From RB7 pin T1OSCEN TTL Buffer RD TRISB Q Set RBIF From other RB7:RB4 pins D EN RD PORTB Q Schmitt Trigger Q1 D RD PORTB EN Q3 PGC T13CKI Note 1: 2: I/O pins have diode protection to VDD and VSS.
PIC18F1220/1320 FIGURE 10-14: BLOCK DIAGRAM OF RB7/PGD/T1OSI/P1D/KBI3 PIN VDD ECCP1 P1C/D Enable RBPU(2) Weak P Pull-up P1B/D Tri-State Auto-Shutdown P1D Data To RB6 pin 1 0 RD LATB Data Bus WR LATB or PORTB D Q RB7 pin CK Q Data Latch D WR TRISB CK Q Q TRIS Latch T1OSCEN TTL Input Buffer RD TRISB Q Set RBIF From other RB7:RB4 pins D EN RD PORTB Q Schmitt Trigger Q1 D RD PORTB EN Q3 PGD Note 1: 2: I/O pins have diode protection to VDD and VSS.
PIC18F1220/1320 TABLE 10-3: PORTB FUNCTIONS Name Bit# Buffer RB0/AN4/INT0 bit 0 TTL(1)/ST(2) Input/output port pin, analog input or external interrupt input 0. RB1/AN5/TX/CK/INT1 bit 1 TTL(1)/ST(2) Input/output port pin, analog input, Enhanced USART Asynchronous Transmit, Addressable USART Synchronous Clock or external interrupt input 1. RB2/P1B/INT2 bit 2 TTL(1)/ST(2) Input/output port pin or external interrupt input 2. Internal software programmable weak pull-up.
PIC18F1220/1320 11.
PIC18F1220/1320 FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE Data Bus FOSC/4 RA4/T0CKI pin 0 8 1 Sync with Internal Clocks 1 Programmable Prescaler TMR0 0 (2 TCY Delay) T0SE 3 PSA Set Interrupt Flag bit TMR0IF on Overflow T0PS2, T0PS1, T0PS0 T0CS Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
PIC18F1220/1320 11.1 11.2.1 Timer0 Operation SWITCHING PRESCALER ASSIGNMENT Timer0 can operate as a timer or as a counter. The prescaler assignment is fully under software control (i.e., it can be changed “on-the-fly” during program execution). Timer mode is selected by clearing the T0CS bit. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles.
PIC18F1220/1320 NOTES: DS39605F-page 102 © 2007 Microchip Technology Inc.
PIC18F1220/1320 12.0 TIMER1 MODULE The Timer1 module timer/counter has the following features: • 16-bit timer/counter (two 8-bit registers: TMR1H and TMR1L) • Readable and writable (both registers) • Internal or external clock select • Interrupt-on-overflow from FFFFh to 0000h • Reset from CCP module special event trigger • Status of system clock operation Figure 12-1 is a simplified block diagram of the Timer1 module. REGISTER 12-1: Register 12-1 details the Timer1 Control register.
PIC18F1220/1320 12.1 Timer1 Operation When TMR1CS = 0, Timer1 increments every instruction cycle. When TMR1CS = 1, Timer1 increments on every rising edge of the external clock input, or the Timer1 oscillator, if enabled. Timer1 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter When the Timer1 oscillator is enabled (T1OSCEN is set), the RB7/PGD/T1OSI/P1D/KBI3 and RB6/T1OSO/ T13CKI/P1C/KBI2 pins become inputs.
PIC18F1220/1320 12.2 Timer1 Oscillator FIGURE 12-3: A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit, T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator rated for 32 kHz crystals. It will continue to run during all power managed modes. The circuit for a typical LP oscillator is shown in Figure 12-3. Table 12-1 shows the capacitor selection for the Timer1 oscillator.
PIC18F1220/1320 12.3 Timer1 Oscillator Layout Considerations 12.5 The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 12-3, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD.
PIC18F1220/1320 12.7 Using Timer1 as a Real-Time Clock Adding an external LP oscillator to Timer1 (such as the one described in Section 12.2 “Timer1 Oscillator”, above), gives users the option to include RTC functionality to their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time.
PIC18F1220/1320 TABLE 12-2: Name REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 IPR1 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP -111 -111 -111 -111 INTCON GIE/GIEH PEIE/GIEL TMR1L
PIC18F1220/1320 13.0 TIMER2 MODULE 13.1 The Timer2 module timer has the following features: • • • • • • 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match with PR2 Timer2 has a control register shown in Register 13-1. TMR2 can be shut off by clearing control bit, TMR2ON (T2CON<2>), to minimize power consumption.
PIC18F1220/1320 13.2 Timer2 Interrupt 13.3 The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. FIGURE 13-1: Output of TMR2 The output of TMR2 (before the postscaler) is fed to the Synchronous Serial Port module, which optionally uses it to generate the shift clock.
PIC18F1220/1320 14.0 TIMER3 MODULE Figure 14-1 is a simplified block diagram of the Timer3 module. The Timer3 module timer/counter has the following features: • 16-bit timer/counter (two 8-bit registers; TMR3H and TMR3L) • Readable and writable (both registers) • Internal or external clock select • Interrupt-on-overflow from FFFFh to 0000h • Reset from CCP module trigger REGISTER 14-1: Register 14-1 shows the Timer3 Control register.
PIC18F1220/1320 14.1 Timer3 Operation When TMR3CS = 0, Timer3 increments every instruction cycle. When TMR3CS = 1, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer3 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter When the Timer1 oscillator is enabled (T1OSCEN is set), the RB7/PGD/T1OSI/P1D/KBI3 and RB6/PGC/ T1OSO/T13CKI/P1C/KBI2 pins become inputs.
PIC18F1220/1320 14.2 Timer1 Oscillator 14.4 The Timer1 oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting the T1OSCEN (T1CON<3>) bit. The oscillator is a lowpower oscillator rated for 32 kHz crystals. See Section 12.2 “Timer1 Oscillator” for further details. 14.3 If the CCP module is configured in Compare mode to generate a “special event trigger” (CCP1M3:CCP1M0 = 1011), this signal will reset Timer3. See Section 15.4.
PIC18F1220/1320 NOTES: DS39605F-page 114 © 2007 Microchip Technology Inc.
PIC18F1220/1320 15.0 ENHANCED CAPTURE/ COMPARE/PWM (ECCP) MODULE The control register for CCP1 is shown in Register 15-1. The Enhanced CCP module is implemented as a standard CCP module with Enhanced PWM capabilities. These capabilities allow for 2 or 4 output channels, user-selectable polarity, dead-band control and automatic shutdown and restart and are discussed in detail in Section 15.5 “Enhanced PWM Mode”.
PIC18F1220/1320 15.1 ECCP Outputs The Enhanced CCP module may have up to four outputs, depending on the selected operating mode. These outputs, designated P1A through P1D, are multiplexed with I/O pins on PORTB. The pin assignments are summarized in Table 15-1. TABLE 15-1: To configure I/O pins as PWM outputs, the proper PWM mode must be selected by setting the P1Mn and CCP1Mn bits (CCP1CON<7:6> and <3:0>, respectively). The appropriate TRISB direction bits for the port pins must also be set as outputs.
PIC18F1220/1320 15.3.4 CCP PRESCALER There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off or the CCP module is not in Capture mode, the prescaler counter is cleared. This means that any Reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler.
PIC18F1220/1320 FIGURE 15-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger will: Reset Timer1 or Timer3, but does not set Timer1 or Timer3 interrupt flag bit and set bit GO/DONE (ADCON0<2>), which starts an A/D conversion.
PIC18F1220/1320 15.5 Enhanced PWM Mode 15.5.2 The Enhanced PWM Mode provides additional PWM output options for a broader range of control applications. The module is an upwardly compatible version of the standard CCP module and offers up to four outputs, designated P1A through P1D. Users are also able to select the polarity of the signal (either active-high or active-low).
PIC18F1220/1320 FIGURE 15-3: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE CCP1CON<5:4> Duty Cycle Registers CCP1M<3:0> 4 P1M1<1:0> 2 CCPR1L CCP1/P1A RB3/CCP1/P1A TRISB<3> CCPR1H (Slave) P1B R Comparator Output Controller Q RB2/P1B/INT2 TRISB<2> RB6/PGC/T1OSO/T13CKI/ P1C/KBI2 P1C TMR2 (Note 1) TRISB<6> S P1D Comparator Clear Timer, set CCP1 pin and latch D.C.
PIC18F1220/1320 FIGURE 15-5: PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) 0 CCP1CON<7:6> PR2+1 Duty Cycle SIGNAL Period 00 (Single Output) P1A Modulated P1A Modulated 10 (Half-Bridge) Delay(1) Delay(1) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Duty Cycle = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (
PIC18F1220/1320 15.5.4 HALF-BRIDGE MODE The TRISB<3> and TRISB<2> bits must be cleared to configure P1A and P1B as outputs. In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the RB3/CCP1/P1A pin, while the complementary PWM output signal is output on the RB2/P1B/INT2 pin (Figure 15-6).
PIC18F1220/1320 15.5.5 FULL-BRIDGE MODE In Full-Bridge Output mode, four pins are used as outputs; however, only two outputs are active at a time. In the Forward mode, pin RB3/CCP1/P1A is continuously active and pin RB7/PGD/T1OSI/P1D/KBI3 is modulated. In the Reverse mode, pin RB6/PGC/ T1OSO/T13CKI/P1C/KBI2 is continuously active and pin RB2/P1B/INT2 is modulated. These are illustrated in Figure 15-8.
PIC18F1220/1320 FIGURE 15-9: EXAMPLE OF FULL-BRIDGE APPLICATION V+ PIC18F1220/1320 FET Driver QC QA FET Driver P1A Load P1B FET Driver P1C FET Driver QD QB VP1D 15.5.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows the user to control the Forward/Reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle.
PIC18F1220/1320 FIGURE 15-10: PWM DIRECTION CHANGE (ACTIVE-HIGH) PWM Period(1) SIGNAL PWM Period P1A P1B DC P1C One Timer2 Count(2) P1D DC Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C toggle one Timer2 count before the end of the current PWM cycle. The modulated P1B and P1D signals are inactive at this time.
PIC18F1220/1320 15.5.6 PROGRAMMABLE DEAD-BAND DELAY In half-bridge applications where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period of time until one switch completely turns off.
PIC18F1220/1320 REGISTER 15-3: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM/AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 R/W-0 R/W-0 R/W-0 R/W-0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 bit 7 bit 0 bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit 0 = ECCP outputs are operating 1 = A shutdown event has occurred; ECCP outputs are in shutdown state bit 6 ECCPAS2: ECCP Auto-Shutdown bit 2 0 = INT0 pin has no effect 1 = INT0 pin low causes shutdown bit 5 ECCPAS1: ECCP
PIC18F1220/1320 15.5.7.1 Auto-Shutdown and Automatic Restart The auto-shutdown feature can be configured to allow automatic restarts of the module, following a shutdown event. This is enabled by setting the PRSEN bit of the PWM1CON register (PWM1CON<7>). In Shutdown mode with PRSEN = 1 (Figure 15-12), the ECCPASE bit will remain set for as long as the cause of the shutdown continues. When the shutdown condition clears, the ECCPASE bit is automatically cleared.
PIC18F1220/1320 15.5.9 SETUP FOR PWM OPERATION The following steps should be taken when configuring the ECCP1 module for PWM operation: 1. 2. 3. 4. 5. 6. 7. 8. 9. Configure the PWM pins P1A and P1B (and P1C and P1D, if used) as inputs by setting the corresponding TRISB bits. Set the PWM period by loading the PR2 register.
PIC18F1220/1320 TABLE 15-5: Name INTCON RCON REGISTERS ASSOCIATED WITH ENHANCED PWM AND TIMER2 Bit 7 Bit 6 GIE/GIEH PEIE/GIEL IPEN — Value on all other Resets Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u — RI TO PD POR BOR 0--1 11qq 0--q qquu -000 -000 -000 -000 PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 — ADIP RCIP TXIP — CC
PIC18F1220/1320 16.0 ENHANCED ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The Enhanced Addressable Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers.
PIC18F1220/1320 REGISTER 16-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care.
PIC18F1220/1320 REGISTER 16-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care.
PIC18F1220/1320 REGISTER 16-3: BAUDCTL: BAUD RATE CONTROL REGISTER U-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 — RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receiver is Idle 0 = Receiver is busy bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: Unused in this mode.
PIC18F1220/1320 16.2 16.2.1 EUSART Baud Rate Generator (BRG) The BRG is a dedicated 8-bit or 16-bit generator, that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCTL<3>) selects 16-bit mode. The SPBRGH:SPBRG register pair controls the period of a free running timer. In Asynchronous mode, bits BRGH (TXSTA<2>) and BRG16 also control the baud rate. In Synchronous mode, bit BRGH is ignored.
PIC18F1220/1320 TABLE 16-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 -010 0000 -010 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x — RCIDL — SCKP BRG16 — WUE ABDEN -1-1 0-00 -1-1 0-00 Name BAUDCTL SPBRGH Baud Rate Generator Register High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Regist
PIC18F1220/1320 TABLE 16-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) % Error FOSC = 20.000 MHz SPBRG value (decimal) Actual Rate (K) % Error FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error SPBRG value FOSC = 8.000 MHz (decimal) Actual Rate (K) % Error SPBRG value SPBRG value (decimal) 2.4 — — — — — — 2.441 1.73 255 2403 -0.16 207 9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.
PIC18F1220/1320 TABLE 16-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error 0.00 0.00 33332 8332 0.300 1.200 0.02 4165 Actual Rate (K) % Error 0.3 1.2 0.300 1.200 2.4 2.400 SPBRG value FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error 0.00 0.02 16665 4165 0.300 1.200 2.400 0.02 2082 2.402 SPBRG value FOSC = 8.
PIC18F1220/1320 16.2.3 AUTO-BAUD RATE DETECT Note 1: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible due to bit error rates. Overall system timing and communication baud rates must be taken into consideration when using the Auto-Baud Rate Detection feature. The Enhanced USART module supports the automatic detection and calibration of baud rate.
PIC18F1220/1320 FIGURE 16-1: BRG Value AUTOMATIC BAUD RATE CALCULATION XXXXh RX pin 0000h 001Ch Start Edge #1 Bit 1 Bit 0 Edge #2 Bit 3 Bit 2 Edge #3 Bit 5 Bit 4 Edge #4 Bit 7 Bit 6 Edge #5 Stop Bit BRG Clock Auto-Cleared Set by User ABDEN bit RCIF bit (Interrupt) Read RCREG SPBRG XXXXh 1Ch SPBRGH XXXXh 00h Note 1: 16.3 The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
PIC18F1220/1320 To set up an Asynchronous Transmission: 1. 2. 3. 4. 5. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit. FIGURE 16-2: 6. 7.
PIC18F1220/1320 FIGURE 16-4: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG Word 2 Word 1 BRG Output (Shift Clock) RB1/AN5/TX/ CK/INT1 (pin) Start bit bit 0 bit 1 Word 1 1 TCY TXIF bit (Interrupt Reg. Flag) bit 7/8 Stop bit Start bit Word 2 bit 0 1 TCY TRMT bit (Transmit Shift Reg. Empty Flag) Note: INTCON Word 2 Transmit Shift Reg. This timing diagram shows two consecutive transmissions. TABLE 16-5: Name Word 1 Transmit Shift Reg.
PIC18F1220/1320 16.3.2 EUSART ASYNCHRONOUS RECEIVER 16.3.3 The receiver block diagram is shown in Figure 16-5. The data is received on the RB4/AN6/RX/DT/KBI0 pin and drives the data recovery block. The data recovery block is actually a high-speed shifter, operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems.
PIC18F1220/1320 To set up an Asynchronous Transmission: 1. 2. 3. 4. 5. Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, set bit BRGH (see Section 16.2 “EUSART Baud Rate Generator (BRG)”). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit.
PIC18F1220/1320 16.3.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake-up due to activity on the RX/DT line while the EUSART is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCTL<1>).
PIC18F1220/1320 16.3.5 BREAK CHARACTER SEQUENCE The Enhanced USART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. The Break character transmit consists of a Start bit, followed by twelve ‘0’ bits and a Stop bit. The Frame Break character is sent whenever the SENDB and TXEN bits (TXSTA<3> and TXSTA<5>) are set while the Transmit Shift register is loaded with data.
PIC18F1220/1320 16.3.6.2 Receiving a Break Sync 7. 8. To receive a Break Sync: 1. 2. 3. 4. 5. 6. Configure the EUSART for asynchronous transmit and receive. TXEN should remain clear. SPBRGH:SPBRG may be left as is. Enable auto-wake-up. Set WUE. Enable RXIF interrupts. Set RCIE, PEIE, GIE. The controller may be placed in any power managed mode. An RCIF will be generated at the beginning of the Break signal. When the interrupt is received, read RCREG to clear RCIF and discard.
PIC18F1220/1320 16.4 EUSART Synchronous Master Mode Once the TXREG register transfers the data to the TSR register (occurs in one TCYCLE), the TXREG is empty and interrupt bit, TXIF (PIR1<4>), is set. The interrupt can be enabled/disabled by setting/clearing enable bit, TXIE (PIE1<4>). Flag bit, TXIF, will be set, regardless of the state of enable bit, TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register.
PIC18F1220/1320 FIGURE 16-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) bit 0 RB4/AN6/RX/DT/KBI0 pin bit 2 bit 1 bit 6 bit 7 RB1/AN5/TX/CK/INT1 pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 16-7: Name INTCON REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 — ADIF RCIF TXIF — CCP1IF
PIC18F1220/1320 16.4.2 EUSART SYNCHRONOUS MASTER RECEPTION 3. 4. 5. 6. Ensure bits CREN and SREN are clear. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit, RCIF, will be set when reception is complete and an interrupt will be generated if the enable bit, RCIE, was set. 8.
PIC18F1220/1320 TABLE 16-8: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets 0000 000u TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP -111 -111 -111 -111 SPEN RX9 SREN CREN ADDEN FER
PIC18F1220/1320 16.5 EUSART Synchronous Slave Mode To set up a Synchronous Slave Transmission: 1. Synchronous Slave mode is entered by clearing bit, CSRC (TXSTA<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the RB1/AN5/TX/CK/INT1 pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 16.5.
PIC18F1220/1320 16.5.2 EUSART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep, or any Idle mode and bit SREN, which is a “don’t care” in Slave mode. 2. 3. 4. 5. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode.
PIC18F1220/1320 NOTES: DS39605F-page 154 © 2007 Microchip Technology Inc.
PIC18F1220/1320 17.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The module has five registers: • • • • • The Analog-to-Digital (A/D) converter module has seven inputs for the PIC18F1220/1320 devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number. A new feature for the A/D converter is the addition of programmable acquisition time. This feature allows the user to select a new channel for conversion and to set the GO/DONE bit immediately.
PIC18F1220/1320 REGISTER 17-2: ADCON1: A/D CONTROL REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 PCFG6: A/D Port Configuration bit – AN6 1 = Pin configured as a digital port 0 = Pin configured as an analog channel – digital input disabled and reads ‘0’ bit 5 PCFG5: A/D Port Configuration bit – AN5 1 = Pin configured as a digital port 0 = Pin configured as an analog channel – digi
PIC18F1220/1320 REGISTER 17-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT2:ACQT0: A/D Acquisition Time Select bits 000 = 0 TAD(1) 001 = 2 TAD 010 = 4 TAD 011 = 6 TAD 100 = 8 TAD 101 = 12 TAD 110 = 16 TAD 111 = 20 TAD bit 2-0 ADCS2:ADCS0: A/D Conversion Clock Select bits
PIC18F1220/1320 The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (AVDD and AVSS), or the voltage level on the RA3/AN3/VREF+ and RA2/AN2/VREF- pins. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. Each port pin associated with the A/D converter can be configured as an analog input, or as a digital I/O.
PIC18F1220/1320 The value in the ADRESH/ADRESL registers is not modified for a Power-on Reset. The ADRESH/ADRESL registers will contain unknown data after a Power-on Reset. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 17.1 “A/D Acquisition Requirements”.
PIC18F1220/1320 17.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 17-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD).
PIC18F1220/1320 17.3 Selecting and Configuring Automatic Acquisition Time The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit.
PIC18F1220/1320 17.5 Operation in Low-Power Modes The selection of the automatic acquisition time and the A/D conversion clock is determined, in part, by the lowpower mode clock source and frequency while in a low-power mode. If the A/D is expected to operate while the device is in a low-power mode, the ACQT2:ACQT0 and ADCS2:ADCS0 bits in ADCON2 should be updated in accordance with the low-power mode clock that will be used.
PIC18F1220/1320 17.7 A/D Conversions Figure 17-3 shows the operation of the A/D converter after the GO bit has been set and the ACQT2:ACQT0 bits are cleared. A conversion is started after the following instruction to allow entry into Low-Power Sleep mode before the conversion begins. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample.
PIC18F1220/1320 17.8 Use of the CCP1 Trigger software overhead (moving ADRESH/ADRESL to the desired location). The appropriate analog input channel must be selected and the minimum acquisition period is either timed by the user, or an appropriate TACQ time selected before the “special event trigger” sets the GO/DONE bit (starts a conversion). An A/D conversion can be started by the “special event trigger” of the CCP1 module.
PIC18F1220/1320 18.0 LOW-VOLTAGE DETECT In many applications, the ability to determine if the device voltage (VDD) is below a specified voltage level is a desirable feature. A window of operation for the application can be created, where the application software can do “housekeeping tasks”, before the device voltage exits the valid operating range. This can be done using the Low-Voltage Detect module. This module is a software programmable circuitry, where a device voltage trip point can be specified.
PIC18F1220/1320 FIGURE 18-2: LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM LVDIN LVD Control Register 16-to-1 MUX VDD Internally Generated Reference Voltage 1.2V LVDEN The LVD module has an additional feature that allows the user to supply the trip voltage to the module from an external source. This mode is enabled when bits, LVDL3:LVDL0, are set to ‘1111’. In this state, the comparator input is multiplexed from the external input pin, FIGURE 18-3: LVDIF LVDIN (Figure 18-3).
PIC18F1220/1320 18.1 Control Register The Low-Voltage Detect Control register controls the operation of the Low-Voltage Detect circuitry.
PIC18F1220/1320 18.2 Operation The following steps are needed to set up the LVD module: Depending on the power source for the device voltage, the voltage normally decreases relatively slowly. This means that the LVD module does not need to be constantly operating. To decrease the current requirements, the LVD circuitry only needs to be enabled for short periods, where the voltage is checked. After doing the check, the LVD module may be disabled. 1. 2. 3.
PIC18F1220/1320 18.2.1 REFERENCE VOLTAGE SET POINT The internal reference voltage of the LVD module may be used by other internal circuitry (the programmable Brown-out Reset). If these circuits are disabled (lower current consumption), the reference voltage circuit requires a time to become stable before a low-voltage condition can be reliably detected. This time is invariant of system clock speed. This start-up time is specified in electrical specification parameter 36.
PIC18F1220/1320 NOTES: DS39605F-page 170 © 2007 Microchip Technology Inc.
PIC18F1220/1320 19.0 SPECIAL FEATURES OF THE CPU PIC18F1220/1320 devices include several features intended to maximize system reliability, minimize cost through elimination of external components and offer code protection.
PIC18F1220/1320 REGISTER 19-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-1 R/P-1 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 IESO FSCM — — FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 bit 7 IESO: Internal External Switchover bit 1 = Internal External Switchover mode enabled 0 = Internal External Switchover mode disabled bit 6 FSCM: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled bit 5-4 Unimplemented: Read as ‘0’ bit 3-
PIC18F1220/1320 REGISTER 19-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — BORV1 BORV0 BOR PWRTEN bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits 11 = Reserved 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.
PIC18F1220/1320 REGISTER 19-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1
PIC18F1220/1320 REGISTER 19-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 MCLRE — — — — — — — bit 7 bit 0 bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled, RA5 input pin disabled 0 = RA5 input pin enabled, MCLR disabled bit 6-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed REGISTER 19-5: U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state
PIC18F1220/1320 REGISTER 19-6: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — — — CP1 CP0 bit 7 bit 0 bit 7-2 Unimplemented: Read as ‘0’ bit 1 CP1: Code Protection bit (PIC18F1320) 1 = Block 1 (001000-001FFFh) not code-protected 0 = Block 1 (001000-001FFFh) code-protected bit 0 CP0: Code Protection bit (PIC18F1320) 1 = Block 0 (00200-000FFFh) not code-protected 0 = Block 0 (00200-000FFFh) code-protected bit 1 CP1: Code
PIC18F1220/1320 REGISTER 19-8: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) U-0 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 — — — — — — WRT1 WRT0 bit 7 bit 0 bit 7-2 Unimplemented: Read as ‘0’ bit 1 WRT1: Write Protection bit (PIC18F1320) 1 = Block 1 (001000-001FFFh) not write-protected 0 = Block 1 (001000-001FFFh) write-protected bit 0 WRT0: Write Protection bit (PIC18F1320) 1 = Block 0 (00200-000FFFh) not write-protected 0 = Block 0 (00200-000FFFh) write-protected bit 1 WRT1
PIC18F1220/1320 REGISTER 19-10: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) U-0 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 — — — — — — EBTR1 EBTR0 bit 7 bit 0 bit 7-2 Unimplemented: Read as ‘0’ bit 1 EBTR1: Table Read Protection bit (PIC18F1320) 1 = Block 1 (001000-001FFFh) not protected from table reads executed in other blocks 0 = Block 1 (001000-001FFFh) protected from table reads executed in other blocks bit 0 EBTR0: Table Read Protection bit (PIC18F1320) 1 = Block 0 (00200
PIC18F1220/1320 REGISTER 19-12: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F1220/1320 DEVICES R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 bit 7-5 DEV2:DEV0: Device ID bits 111 = PIC18F1220 110 = PIC18F1320 bit 4-0 REV4:REV0: Revision ID bits These bits are used to indicate the device revision.
PIC18F1220/1320 19.2 Watchdog Timer (WDT) Note 1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts when executed. For PIC18F1220/1320 devices, the WDT is driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler.
PIC18F1220/1320 TABLE 19-2: Name CONFIG2H RCON WDTCON Legend: 19.3 SUMMARY OF WATCHDOG TIMER REGISTERS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — — WDTPS3 WDTPS2 WDTPS2 WDTPS0 WDTEN IPEN — — RI TO PD POR BOR — — — — — — — SWDTEN Shaded cells are not used by the Watchdog Timer. Two-Speed Start-up In all other power managed modes, Two-Speed Start-up is not used.
PIC18F1220/1320 19.4 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation, in the event of an external oscillator failure, by automatically switching the system clock to the internal oscillator block. The FSCM function is enabled by setting the Fail-Safe Clock Monitor Enable bit, FSCM (CONFIG1H<6>).
PIC18F1220/1320 19.4.2 EXITING FAIL-SAFE OPERATION The Fail-Safe condition is terminated by either a device Reset, or by entering a power managed mode. On Reset, the controller starts the primary clock source specified in Configuration Register 1H (with any required start-up delays that are required for the oscillator mode, such as OST or PLL timer). The INTOSC multiplexer provides the system clock until the primary clock source becomes ready (similar to a TwoSpeed Start-up).
PIC18F1220/1320 19.4.4 POR OR WAKE FROM SLEEP The FSCM is designed to detect oscillator failure at any point after the device has exited Power-on Reset (POR) or Low-Power Sleep mode. When the primary system clock is EC, RC or INTRC modes, monitoring can begin immediately following these events. For oscillator modes involving a crystal or resonator (HS, HSPLL, LP or XT), the situation is somewhat different.
PIC18F1220/1320 19.5 Program Verification and Code Protection Each of the three blocks has three protection bits associated with them. They are: The overall structure of the code protection on the PIC18 Flash devices differs significantly from other PIC devices. • Code-Protect bit (CPn) • Write-Protect bit (WRTn) • External Block Table Read bit (EBTRn) The user program memory is divided into three blocks. One of these is a boot block of 512 bytes.
PIC18F1220/1320 19.5.1 PROGRAM MEMORY CODE PROTECTION Note: The program memory may be read to, or written from, any location using the table read and table write instructions. The device ID may be read with table reads. The configuration registers may be read and written with the table read and table write instructions. In normal execution mode, the CPn bits have no direct effect. CPn bits inhibit external reads and writes.
PIC18F1220/1320 FIGURE 19-7: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED: PIC18F1320 Register Values Program Memory Configuration Bit Settings 000000h WRTB, EBTRB = 11 0001FFh 000200h TBLPTR = 0002FFh WRT0, EBTR0 = 10 000FFFh 001000h PC = 001FFEh TBLRD * WRT1, EBTR1 = 11 001FFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. TABLAT register returns a value of ‘0’.
PIC18F1220/1320 19.5.2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits external writes to data EEPROM. The CPU can continue to read and write data EEPROM, regardless of the protection bit settings. 19.5.3 CONFIGURATION REGISTER PROTECTION The configuration registers can be write-protected. The WRTC bit controls protection of the configuration registers.
PIC18F1220/1320 19.9 Low-Voltage ICSP Programming The LVP bit in configuration register, CONFIG4L, enables Low-Voltage Programming (LVP). When LVP is enabled, the microcontroller can be programmed without requiring high voltage being applied to the MCLR/VPP/RA5 pin, but the RB5/PGM/KBI1 pin is then dedicated to controlling Program mode entry and is not available as a general purpose I/O pin. LVP is enabled in erased devices.
PIC18F1220/1320 NOTES: DS39605F-page 190 © 2007 Microchip Technology Inc.
PIC18F1220/1320 20.0 INSTRUCTION SET SUMMARY The PIC18 instruction set adds many enhancements to the previous PIC instruction sets, while maintaining an easy migration from these PIC instruction sets. Most instructions are a single program memory word (16 bits), but there are three instructions that require two program memory locations.
PIC18F1220/1320 TABLE 20-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. d Destination select bit d = 0: store result in WREG d = 1: store result in file register f dest Destination either the WREG register or the specified register file location.
PIC18F1220/1320 FIGURE 20-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 8 7 OPCODE d a Example Instruction 0 ADDWF MYREG, W, B f (FILE #) d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 0 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE #) 1111 f
PIC18F1220/1320 TABLE 20-1: PIC18FXXXX INSTRUCTION SET Mnemonic, Operands 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d,
PIC18F1220/1320 TABLE 20-1: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes CONTROL OPERATIONS BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL n n n n n n n n n n, s NOP NOP POP PUSH RCALL RESET RETFIE — — — — n s Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Call subroutine 1st word 2nd word C
PIC18F1220/1320 TABLE 20-1: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add literal and WREG AND literal with WREG Inclusive OR literal with WREG Move literal (12-bit) 2nd word to FSRx 1st word Move literal to BSR<3:0> Move literal to WREG Multiply literal with WREG Return with literal in WREG Subtract WREG fro
PIC18F1220/1320 20.2 Instruction Set ADDLW ADD literal to W Syntax: [ label ] ADDLW Operands: 0 ≤ k ≤ 255 Operation: (W) + k → W Status Affected: N, OV, C, DC, Z Encoding: 0000 Description: 1111 kkkk kkkk The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
PIC18F1220/1320 ADDWFC ADD W and Carry bit to f ANDLW AND literal with W Syntax: [ label ] ADDWFC Syntax: [ label ] ANDLW Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] f [,d [,a]] Operation: (W) + (f) + (C) → dest Status Affected: N, OV, C, DC, Z Encoding: 0010 Description: 1 Cycles: 1 0 ≤ k ≤ 255 Operation: (W) .AND. k → W Status Affected: N, Z Encoding: ffff ffff Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W.
PIC18F1220/1320 ANDWF AND W with f Syntax: [ label ] ANDWF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] f [,d [,a]] Operation: (W) .AND.
PIC18F1220/1320 BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operation: 0 → f Status Affected: None Encoding: Description: Syntax: [ label ] BN Operands: -128 ≤ n ≤ 127 Operation: if Negative bit is ‘1’ (PC) + 2 + 2n → PC Status Affected: None bbba ffff ffff 1110 1 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Read register ‘f’ Process Data Write register ‘f’ BCF FLAG_REG = 0xC7 = 0x47 After Instruction FLAG_REG 0110 nnnn nnnn If the Negative bit
PIC18F1220/1320 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: [ label ] BNC Syntax: [ label ] BNN Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Carry bit is ‘0’ (PC) + 2 + 2n → PC Operation: if Negative bit is ‘0’ (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 n 0011 nnnn nnnn Encoding: 1110 n 0111 nnnn nnnn Description: If the Carry bit is ‘0’, then the program will branch.
PIC18F1220/1320 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: [ label ] BNOV Syntax: [ label ] BNZ Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘0’ (PC) + 2 + 2n → PC Operation: if Zero bit is ‘0’ (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 n 0101 nnnn nnnn Encoding: 1110 n 0001 nnnn nnnn Description: If the Overflow bit is ‘0’, then the program will branch.
PIC18F1220/1320 BRA Unconditional Branch BSF Bit Set f Syntax: [ label ] BRA Syntax: [ label ] BSF Operands: -1024 ≤ n ≤ 1023 Operands: Operation: (PC) + 2 + 2n → PC Status Affected: None 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operation: 1 → f Status Affected: None Encoding: Description: 1101 1 Cycles: 2 Q Cycle Activity: Q1 No operation 0nnn nnnn nnnn Add the 2’s complement number ‘2n’ to the PC.
PIC18F1220/1320 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: [ label ] BTFSC f,b[,a] Syntax: [ label ] BTFSS f,b[,a] Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operands: 0 ≤ f ≤ 255 0≤b<7 a ∈ [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped.
PIC18F1220/1320 BTG Bit Toggle f BOV Branch if Overflow Syntax: [ label ] BTG f,b[,a] Syntax: [ label ] BOV Operands: 0 ≤ f ≤ 255 0≤b<7 a ∈ [0,1] Operands: -128 ≤ n ≤ 127 Operation: if Overflow bit is ‘1’ (PC) + 2 + 2n → PC Status Affected: None Operation: (f) → f Status Affected: None Encoding: Description: bbba ffff 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Read register ‘f’ Process Data Write register ‘f’ Example: BTG PORTB, = 0111 0101 [0x75] After Instruction
PIC18F1220/1320 BZ Branch if Zero CALL Subroutine Call Syntax: [ label ] BZ Syntax: [ label ] CALL k [,s] Operands: -128 ≤ n ≤ 127 Operands: Operation: if Zero bit is ‘1’ (PC) + 2 + 2n → PC 0 ≤ k ≤ 1048575 s ∈ [0,1] Operation: (PC) + 4 → TOS, k → PC<20:1>, if s = 1 (W) → WS, (Status) → STATUSS, (BSR) → BSRS Status Affected: None Status Affected: n None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is ‘1’, then the program will branch.
PIC18F1220/1320 CLRF Clear f Syntax: [ label ] CLRF Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: 000h → f 1→Z Status Affected: Z Encoding: Description: 0110 f [,a] 101a ffff ffff CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 000h → WDT, 000h → WDT postscaler, 1 → TO, 1 → PD Status Affected: TO, PD Encoding: 0000 0000 0000 0100 Clears the contents of the specified register. If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value.
PIC18F1220/1320 COMF Complement f Syntax: [ label ] COMF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest Status Affected: N, Z Encoding: 0001 Description: 1 Cycles: 1 Q Cycle Activity: Q1 Decode ffff Compare f with W, skip if f = W Syntax: [ label ] CPFSEQ Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None Encoding: 0110 001a f [,a] ffff ffff Description: Compares the contents of data memory lo
PIC18F1220/1320 CPFSGT Compare f with W, skip if f > W CPFSLT Compare f with W, skip if f < W Syntax: [ label ] CPFSGT Syntax: [ label ] CPFSLT Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) – (W), skip if (f) > (W) (unsigned comparison) Operation: (f) – (W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: Description: 0110 010a f [,a] ffff ffff Compares the contents of data memory location ‘f’ to the con
PIC18F1220/1320 DAW Decimal Adjust W Register DECF Decrement f Syntax: [ label ] DAW Syntax: [ label ] DECF f [,d [,a]] Operands: None Operands: Operation: If [W<3:0> > 9] or [DC = 1] then (W<3:0>) + 6 → W<3:0>; else (W<3:0>) → W<3:0>; 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest Status Affected: C, DC, N, OV, Z If [W<7:4> > 9] or [C = 1] then (W<7:4>) + 6 → W<7:4>; else (W<7:4>) → W<7:4>; Status Affected: Encoding: 0000 0000 0000 1 Cycles: 1 Q2 Q3 Q4 Read register W
PIC18F1220/1320 DECFSZ Decrement f, skip if 0 DCFSNZ Decrement f, skip if not 0 Syntax: [ label ] DECFSZ f [,d [,a]] Syntax: [ label ] DCFSNZ Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, skip if result = 0 Operation: (f) – 1 → dest, skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da f [,d [,a]] ffff ffff Description: The contents of register ‘f’ are
PIC18F1220/1320 GOTO Unconditional Branch INCF Increment f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 1048575 Operands: Operation: k → PC<20:1> Status Affected: None 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description: 1110 1111 GOTO k 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 GOTO allows an unconditional branch anywhere within the entire 2-Mbyte memory range.
PIC18F1220/1320 INCFSZ Increment f, skip if 0 INFSNZ Increment f, skip if not 0 Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest, skip if result = 0 Operation: (f) + 1 → dest, skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0011 INCFSZ 11da f [,d [,a]] ffff ffff Encoding: 0100 INFSNZ 10da f [,d [,a]] ffff ffff Description: The contents of register ‘f’ a
PIC18F1220/1320 IORLW Inclusive OR literal with W IORWF Inclusive OR W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .OR. (f) → dest Status Affected: N, Z IORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .OR.
PIC18F1220/1320 LFSR Load FSR MOVF Move f Syntax: [ label ] Syntax: [ label ] Operands: 0≤f≤2 0 ≤ k ≤ 4095 Operands: Operation: k → FSRf 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Status Affected: None Operation: f → dest Status Affected: N, Z Encoding: LFSR f,k 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the file select register pointed to by ‘f’.
PIC18F1220/1320 MOVFF Move f to f MOVLB Move literal to low nibble in BSR Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ fs ≤ 4095 0 ≤ fd ≤ 4095 Operands: 0 ≤ k ≤ 255 Operation: k → BSR None MOVFF fs,fd Operation: (fs) → fd Status Affected: Status Affected: None Encoding: Encoding: 1st word (source) 2nd word (destin.) 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register ‘fs’ are moved to destination register ‘fd’.
PIC18F1220/1320 MOVLW Move literal to W MOVWF Move W to f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: Operation: k→W 0 ≤ f ≤ 255 a ∈ [0,1] Status Affected: None Operation: (W) → f Status Affected: None Encoding: 0000 Description: MOVLW k 1110 kkkk The eight-bit literal ‘k’ is loaded into W.
PIC18F1220/1320 MULLW Multiply Literal with W MULWF Multiply W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) x (f) → PRODH:PRODL Status Affected: None MULLW k Operands: 0 ≤ k ≤ 255 Operation: (W) x k → PRODH:PRODL Status Affected: None Encoding: Description: 0000 1 Cycles: 1 Q Cycle Activity: Q1 Example: kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’.
PIC18F1220/1320 NEGF Negate f Syntax: [ label ] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] NEGF Operation: (f) + 1 → f Status Affected: N, OV, C, DC, Z Encoding: 0110 Description: 1 Cycles: 1 Q Cycle Activity: Q1 Syntax: [ label ] NOP Operands: None Operation: No operation Status Affected: None 0000 1111 ffff Description: 1 Cycles: 1 Decode 0000 xxxx 0000 xxxx No operation.
PIC18F1220/1320 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: (TOS) → bit bucket Operation: (PC + 2) → TOS Status Affected: None Status Affected: None Encoding: 0000 POP 0000 0000 0110 Encoding: 0000 PUSH 0000 0000 0101 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
PIC18F1220/1320 RCALL Relative Call RESET Reset Syntax: [ label ] RCALL Syntax: [ label ] Operands: Operation: -1024 ≤ n ≤ 1023 Operands: None (PC) + 2 → TOS, (PC) + 2 + 2n → PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: Description: 1101 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack.
PIC18F1220/1320 RETFIE Return from Interrupt RETLW Return Literal to W Syntax: [ label ] Syntax: [ label ] RETFIE [s] RETLW k Operands: s ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (TOS) → PC, 1 → GIE/GIEH or PEIE/GIEL, if s = 1 (WS) → W, (STATUSS) → Status, (BSRS) → BSR, PCLATU, PCLATH are unchanged.
PIC18F1220/1320 RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] RETURN [s] RLCF f [,d [,a]] Operands: s ∈ [0,1] Operands: Operation: (TOS) → PC, if s = 1 (WS) → W, (STATUSS) → Status, (BSRS) → BSR, PCLATU, PCLATH are unchanged 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<7>) → C, (C) → dest<0> Status Affected: C, N, Z None Encoding: Status Affected: Encoding: 0000 0000 0001 001s Description: Return from su
PIC18F1220/1320 RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) → dest, (f<7>) → dest<0> Operation: Status Affected: N, Z (f) → dest, (f<0>) → C, (C) → dest<7> Status Affected: C, N, Z Encoding: 0100 Description: RLNCF 01da f [,d [,a]] ffff ffff The contents of register ‘f’ are rotated one bit to the left.
PIC18F1220/1320 RRNCF Rotate Right f (no carry) SETF Set f Syntax: [ label ] Syntax: [ label ] SETF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) → dest, (f<0>) → dest<7> FFh → f Operation: Status Affected: None Status Affected: N, Z Encoding: 0100 Description: RRNCF 00da f [,d [,a]] Encoding: ffff ffff The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W.
PIC18F1220/1320 SLEEP Enter Sleep mode SUBFWB Subtract f from W with borrow Syntax: [ label ] SLEEP Syntax: [ label ] SUBFWB Operands: None Operands: Operation: 00h → WDT, 0 → WDT postscaler, 1 → TO, 0 → PD 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) – (f) – (C) → dest Status Affected: N, OV, C, DC, Z TO, PD Encoding: Status Affected: Encoding: 0000 0000 0000 0011 Description: The Power-down status bit (PD) is cleared. The Time-out status bit (TO) is set.
PIC18F1220/1320 SUBLW Subtract W from literal SUBWF Subtract W from f Syntax: [ label ] SUBLW k Syntax: [ label ] SUBWF Operands: 0 ≤ k ≤ 255 Operands: Operation: k – (W) → W 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Status Affected: N, OV, C, DC, Z Operation: (f) – (W) → dest Status Affected: N, OV, C, DC, Z Encoding: 0000 Description: 1000 kkkk W is subtracted from the eight-bit literal ‘k’. The result is placed in W.
PIC18F1220/1320 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: [ label ] SUBWFB Syntax: [ label ] SWAPF f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) – (C) → dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) → dest<7:4>, (f<7:4>) → dest<3:0> Status Affected: None Encoding: 0101 Description: 10da f [,d [,a]] ffff ffff Subtract W and the Carry flag (borrow) from register ‘f’ (2’s complement met
PIC18F1220/1320 TBLRD Table Read TBLRD Table Read (Continued) Syntax: [ label ] TBLRD ( *; *+; *-; +*) Example 1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) → TABLAT; TBLPTR – No Change; if TBLRD *+, (Prog Mem (TBLPTR)) → TABLAT; (TBLPTR) + 1 → TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) → TABLAT; (TBLPTR) – 1 → TBLPTR; if TBLRD +*, (TBLPTR) + 1 → TBLPTR; (Prog Mem (TBLPTR)) → TABLAT; Before Instruction Status Affected: None Encoding: Description: 0000 *+ ; 0000 0000 10n
PIC18F1220/1320 TBLWT Table Write TBLWT Syntax: [ label ] TBLWT ( *; *+; *-; +*) Words: 1 Operands: None Cycles: 2 Operation: if TBLWT*, (TABLAT) → Holding Register; TBLPTR – No Change; if TBLWT*+, (TABLAT) → Holding Register; (TBLPTR) + 1 → TBLPTR; if TBLWT*-, (TABLAT) → Holding Register; (TBLPTR) – 1 → TBLPTR; if TBLWT+*, (TBLPTR) + 1 → TBLPTR; (TABLAT) → Holding Register; Q Cycle Activity: Description: 0000 0000 0000 11nn nn = 0* = 1*+ = 2*= 3+* This instruction uses the 3 LSBs of TBLPTR
PIC18F1220/1320 TSTFSZ Test f, skip if 0 XORLW Exclusive OR literal with W Syntax: [ label ] TSTFSZ f [,a] Syntax: [ label ] XORLW k Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: Operation: skip if f = 0 (W) .XOR.
PIC18F1220/1320 XORWF Exclusive OR W with f Syntax: [ label ] XORWF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .XOR. (f) → dest Status Affected: N, Z Encoding: 0001 10da f [,d [,a]] ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank will be selected, overriding the BSR value.
PIC18F1220/1320 21.
PIC18F1220/1320 21.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
PIC18F1220/1320 21.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
PIC18F1220/1320 21.11 PICSTART Plus Development Programmer 21.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
PIC18F1220/1320 22.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR and RA4) .......................................... -0.
PIC18F1220/1320 FIGURE 22-1: PIC18F1220/1320 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18F1X20 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz Frequency FIGURE 22-2: PIC18LF1220/1320 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18LF1X20 Voltage 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz 4 MHz Frequency FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
PIC18F1220/1320 FIGURE 22-3: PIC18F1220/1320 VOLTAGE-FREQUENCY GRAPH (EXTENDED) 6.0V 5.5V Voltage 5.0V PIC18F1X20-E 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 25 MHz Frequency © 2007 Microchip Technology Inc.
PIC18F1220/1320 22.1 DC Characteristics: Supply Voltage PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC18F1220/1320 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC18F1220/1320 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC18F1220/1320 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC18F1220/1320 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC18F1220/1320 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC18F1220/1320 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC18F1220/1320 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC18F1220/1320 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC18F1220/1320 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC18F1220/1320 22.3 DC Characteristics: PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Max Units Conditions VSS 0.15 VDD V VDD < 4.5V — 0.8 V 4.5V ≤ VDD ≤ 5.5V Input Low Voltage I/O ports: D030 with TTL buffer D030A D031 VSS 0.
PIC18F1220/1320 22.3 DC Characteristics: PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param Symbol No. VOL Characteristic Min Max Units Conditions Output Low Voltage D080 I/O ports — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C D083 OSC2/CLKO (RC mode) — 0.6 V IOL = 1.6 mA, VDD = 4.
PIC18F1220/1320 TABLE 22-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial DC CHARACTERISTICS Param No. Sym Characteristic Min Typ† Max Units Conditions Internal Program Memory Programming Specifications(1) D110 VPP Voltage on MCLR/VPP pin 9.00 — 13.
PIC18F1220/1320 FIGURE 22-4: LOW-VOLTAGE DETECT CHARACTERISTICS VDD (LVDIF can be cleared in software) VLVD (LVDIF set by hardware) LVDIF TABLE 22-2: LOW-VOLTAGE DETECT CHARACTERISTICS PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for e
PIC18F1220/1320 TABLE 22-2: LOW-VOLTAGE DETECT CHARACTERISTICS (CONTINUED) PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18F1220/1320 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC18F1220/1320 22.4 22.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC18F1220/1320 22.4.2 TIMING CONDITIONS The temperature and voltages specified in Table 22-3 apply to all timing specifications unless otherwise noted. Figure 22-5 specifies the load conditions for the timing specifications.
PIC18F1220/1320 22.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 22-6: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 22-4: Param. No.
PIC18F1220/1320 TABLE 22-5: Param No. PLL CLOCK TIMING SPECIFICATIONS, HS/HSPLL MODE (VDD = 4.2V TO 5.
PIC18F1220/1320 FIGURE 22-7: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 14 12 18 19 16 I/O pin (Input) 15 17 I/O pin (Output) New Value Old Value 20, 21 Note: Refer to Figure 22-5 for load conditions. TABLE 22-7: CLKO AND I/O TIMING REQUIREMENTS Param. Symbol No.
PIC18F1220/1320 FIGURE 22-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure 22-5 for load conditions. FIGURE 22-9: BROWN-OUT RESET TIMING BVDD VDD 35 VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference Voltage Stable DS39605F-page 260 36 © 2007 Microchip Technology Inc.
PIC18F1220/1320 TABLE 22-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol No. Characteristic Min Typ Max Units 2 — — μs 30 TmcL MCLR Pulse Width (low) 31 TWDT Watchdog Timer Time-out Period (No postscaler) 3.48 4.00 4.71 ms 32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — 33 TPWRT Power-up Timer Period — 65.
PIC18F1220/1320 TABLE 22-9: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol No. Characteristic 40 Tt0H T0CKI High Pulse Width 41 Tt0L T0CKI Low Pulse Width 42 Tt0P T0CKI Period No prescaler Min Max Units 0.5 TCY + 20 — ns With prescaler No prescaler 10 — ns 0.5 TCY + 20 — ns With prescaler With prescaler 45 Tt1H 10 — ns TCY + 10 — ns Greater of: 20 ns or TCY + 40 N — ns No prescaler T13CKI High Time Synchronous, no prescaler 0.
PIC18F1220/1320 TABLE 22-10: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param. Symbol No. 50 TccL Characteristic Min Max Units CCPx Input Low No prescaler Time With prescaler PIC18F1X20 0.5 TCY + 20 — ns 10 — ns 20 — ns 0.
PIC18F1220/1320 FIGURE 22-13: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RB1/AN5/TX/ CK/INT1 pin 125 RB4/AN6/RX/ DT/KBI0 pin 126 Note: Refer to Figure 22-5 for load conditions. TABLE 22-12: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Param. No.
PIC18F1220/1320 FIGURE 22-14: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 A/D CLK(1) 132 9 A/D DATA 8 7 ... ... 2 1 0 NEW_DATA OLD_DATA ADRES TCY ADIF GO DONE Sampling Stopped SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
PIC18F1220/1320 NOTES: DS39605F-page 266 © 2007 Microchip Technology Inc.
PIC18F1220/1320 23.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC18F1220/1320 FIGURE 23-3: MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +125°C 0.7 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0.6 5.5V 5.0V 0.5 4.5V IDD (mA) 0.4 4.0V 0.3 3.5V 3.0V 0.2 2.5V 0.1 2.0V 0.0 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 FOSC (MHz) TYPICAL IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, +25°C FIGURE 23-4: 2.
PIC18F1220/1320 FIGURE 23-5: MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +125°C 2.5 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 2.0 5.5V 5.0V IDD (mA) 1.5 4.5V 4.0V 1.0 3.5V 3.0V 2.5V 0.5 2.0V 0.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) TYPICAL IDD vs.
PIC18F1220/1320 FIGURE 23-7: MAXIMUM IDD vs. FOSC OVER VDD PRI_RUN, EC MODE, -40°C TO +125°C 16 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 14 5.5V 5.0V 12 4.0V 10 IDD (mA) 4.5V 8 3.5V 6 4 3.0V 2 2.5V 2.0V 0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) FIGURE 23-8: TYPICAL IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, +25°C 0.
PIC18F1220/1320 FIGURE 23-9: MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +85°C 0.045 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0.040 5.5V 0.035 5.0V 0.030 IDD (mA) 4.5V 0.025 4.0V 0.020 3.5V 3.0V 0.015 2.5V 0.010 2.0V 0.005 0.000 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 FOSC (MHz) FIGURE 23-10: MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +125°C 0.100 0.
PIC18F1220/1320 FIGURE 23-11: TYPICAL IDD vs. OSC PRI_IDLE, EC MODE, Typical I F vs F OVER over VVDD PRI_IDLE, EC mode, +25°C +25°C 600 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 500 5.5V 5.0V 400 IDD (μA) 4.5V 4.0V 300 3.5V 3.0V 200 2.5V 2.0V 100 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) FIGURE 23-12: MAXIMUM IDD vs.
PIC18F1220/1320 FIGURE 23-13: TYPICAL IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, +25°C 6.0 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 5.5 5.0 4.5 5.5V 4.0 5.0V IDD (mA) 3.5 4.5V 3.0 4.0V 2.5 2.0 3.5V 1.5 3.0V 1.0 2.5V 0.5 2.0V 0.0 4 8 12 16 20 24 28 32 36 40 FOSC (MHz) FIGURE 23-14: MAXIMUM IDD vs. FOSC OVER VDD PRI_IDLE, EC MODE, -40°C TO +125°C 6.0 5.
PIC18F1220/1320 FIGURE 23-15: TYPICAL IPD vs. VDD (+25°C), 125 kHz TO 8 MHz RC_RUN MODE, ALL PERIPHERALS DISABLED 3000 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 8 MHz 2500 250 kHz and 500 kHz curves are bounded by 125 kHz and 1 MHz curves. IPD (μA) 2000 1500 4 MHz 1000 2 MHz 500 1 MHz 125 kHz 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 23-16: MAXIMUM IPD vs.
PIC18F1220/1320 FIGURE 23-17: TYPICAL AND MAXIMUM IPD vs. VDD (-40°C TO +125°C), 31.25 kHz RC_RUN MODE, ALL PERIPHERALS DISABLED 100 Max (+125°C) Max (+85°C) IPD (μA) Typ (+25°C) 10 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 1 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 23-18: TYPICAL IPD vs.
PIC18F1220/1320 FIGURE 23-19: MAXIMUM IPD vs. VDD (-40°C TO +125°C), 125 kHz TO 8 MHz RC_IDLE MODE, ALL PERIPHERALS DISABLED 800 8 MHz 750 250 kHz and 500 kHz curves are bounded by 125 kHz and 1 MHz curves. 700 650 4 MHz 2 MHz 1 MHz 125 kHz 600 550 IPD (μA) 500 450 400 350 300 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 250 200 150 100 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 23-20: TYPICAL AND MAXIMUM IPD vs.
PIC18F1220/1320 FIGURE 23-21: IPD SEC_RUN MODE, -10°C TO +70°C, 32.768 kHz XTAL, 2 x 22 pF, ALL PERIPHERALS DISABLED 80 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 70 60 Max (+70°C) IPD (μA) 50 40 Typ (+25°C) 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.0 5.5 VDD (V) FIGURE 23-22: IPD SEC_IDLE MODE, -10°C TO +70°C, 32.
PIC18F1220/1320 FIGURE 23-23: TOTAL IPD, -40°C TO +125°C SLEEP MODE, ALL PERIPHERALS DISABLED 100 Max (+125°C) 10 Max (+85°C) IPD (μA) 1 0.1 Typ (+25°C) 0.01 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0.001 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 23-24: VOH vs. IOH OVER TEMPERATURE (-40°C TO +125°C), VDD = 3.0V 3.0 2.5 2.0 VOH (V) Max (+125°C) 1.5 Typ (+25°C) Min (+125°C) 1.0 0.5 0.
PIC18F1220/1320 FIGURE 23-25: VOH vs. IOH OVER TEMPERATURE (-40°C TO +125°C), VDD = 5.0V 5.0 4.5 Max (+125°C) 4.0 Typ (+25°C) 3.5 VOH (V) 3.0 2.5 Min (+125°C) 2.0 1.5 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-mA) FIGURE 23-26: VDD = 3.0V VOL vs. IOLV OVER vs I TEMPERATURE over Temp (-40°C to(-40°C +125°C)TO V +125°C), = 3.0V 3.0 Max (+125°C) 2.5 Max (+85°C) VOL (V) 2.0 1.5 Typ (+25°C) 1.0 0.5 Min (+125°C) 0.0 0 5 10 15 20 25 IOL (-mA) © 2007 Microchip Technology Inc.
PIC18F1220/1320 FIGURE 23-27: VOL vs. IOL OVER TEMPERATURE (-40°C TO +125°C), VDD = 5.0V 1.0 0.9 Max (+125°C) 0.8 0.7 0.6 VOL (V) Max (+85°C) 0.5 0.4 Typ (+25°C) 0.3 0.2 Min (+125°C) 0.1 0.0 0 5 10 15 20 25 IOL (-mA) FIGURE 23-28: ΔIPD TIMER1 OSCILLATOR, -10°C TO +70°C SLEEP MODE, TMR1 COUNTER DISABLED IPD Timer1 Oscillator, -10°C to +70°C SLEEP mode, TMR1 counter disabled 5.0 4.5 Max (-10°C to +70°C) 4.0 3.5 3.0 IPD (μA) Typ (+25°C) 2.5 2.0 1.
PIC18F1220/1320 FIGURE 23-29: ΔIPD FSCM vs. VDD OVER TEMPERATURE PRI_IDLE MODE, EC OSCILLATOR AT 32 kHz, -40°C TO +125°C 4.5 4.0 Max (-40°C) 3.5 ΔIPD (μA) 3.0 2.5 Typ (+25°C) 2.0 1.5 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC18F1220/1320 FIGURE 23-31: ΔIPD LVD vs. VDD SLEEP MODE, LVDL3:LVDL0 = 0001 (2V) 50 45 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 40 Max (+125°C) 35 Max (+85°C) IPD (μA) 30 Typ (+25°C) 25 20 15 10 Low-Voltage Detection Range 5 Normal Operating Range 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.0 5.5 VDD (V) FIGURE 23-32: ΔIPD BOR vs.
PIC18F1220/1320 FIGURE 23-33: ΔIPD A/D, -40°C TO +125°C SLEEP MODE, A/D ENABLED (NOT CONVERTING) 10 Max (+125°C) IPD (μA) 1 Max (+85°C) 0.1 0.01 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) Typ (+25°C) 0.001 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 23-34: AVERAGE FOSC vs. VDD FOR VARIOUS R’s EXTERNAL RC MODE, C = 20 pF, TEMPERATURE = +25°C 5.0 Operation above 4 MHz is not recomended 4.5 4.0 5.1K 3.5 Freq (MHz) 3.
PIC18F1220/1320 FIGURE 23-35: AVERAGE FOSC vs. VDD FOR VARIOUS R’s EXTERNAL RC MODE, C = 100 pF, TEMPERATURE = +25°C 2.0 1.8 1.6 5.1K 1.4 Freq (MHz) 1.2 1.0 10K 0.8 0.6 0.4 33K 0.2 100K 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 23-36: AVERAGE FOSC vs. VDD FOR VARIOUS R’s EXTERNAL RC MODE, C = 300 pF, TEMPERATURE = +25°C 0.8 0.7 0.6 Freq (MHz) 0.5 5.1K 0.4 0.3 10K 0.2 0.1 33K 100K 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC18F1220/1320 24.0 PACKAGING INFORMATION 24.1 Package Marking Information 18-Lead PDIP Example PIC18F1320-I/P e3 0710017 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 18-Lead SOIC XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX Example PIC18F1220E/SO e3 0710017 YYWWNNN 20-Lead SSOP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 28-Lead QFN XXXXXXXX XXXXXXXX YYWWNNN Legend: XX...
PIC18F1220/1320 24.2 Package Details The following sections give the technical details of the packages. 18-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c A1 b1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 18 Pitch e Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .
PIC18F1220/1320 18-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 b e α h h c φ A2 A A1 β L L1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 18 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 2.05 – – Standoff § A1 0.10 – 0.
PIC18F1220/1320 20-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 b e c A2 A φ A1 L1 Units Dimension Limits Number of Pins L MILLIMETERS MIN N NOM MAX 20 Pitch e Overall Height A – 0.65 BSC – 2.00 Molded Package Thickness A2 1.65 1.75 1.85 Standoff A1 0.05 – – Overall Width E 7.40 7.80 8.
PIC18F1220/1320 28-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6 mm Body [QFN] with 0.55 mm Contact Length Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D2 EXPOSED PAD e E b E2 2 2 1 1 N K N NOTE 1 L BOTTOM VIEW TOP VIEW A A3 A1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 28 Pitch e Overall Height A 0.80 0.65 BSC 0.90 1.00 Standoff A1 0.00 0.02 0.
PIC18F1220/1320 NOTES: DS39605F-page 290 © 2007 Microchip Technology Inc.
PIC18F1220/1320 APPENDIX A: REVISION HISTORY Revision A (August 2002) Revision F (February 2007) This revision includes updates to the packaging diagrams. Original data sheet for PIC18F1220/1320 devices. Revision B (November 2002) This revision includes significant changes to Section 2.0, Section 3.0 and Section 19.0, as well as updates to the Electrical Specifications in Section 22.0 and includes minor corrections to the data sheet text.
PIC18F1220/1320 APPENDIX C: CONVERSION CONSIDERATIONS This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B. Not Applicable DS39605F-page 292 APPENDIX D: MIGRATION FROM BASELINE TO ENHANCED DEVICES This section discusses how to migrate from a baseline device (i.e.
PIC18F1220/1320 APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN716, “Migrating Designs from PIC16C74A/74B to PIC18C442”. The changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations.
PIC18F1220/1320 NOTES: DS39605F-page 294 © 2007 Microchip Technology Inc.
PIC18F1220/1320 INDEX A A/D ................................................................................... 155 A/D Converter Interrupt, Configuring ....................... 159 Acquisition Requirements ........................................ 160 ADCON0 Register .................................................... 155 ADCON1 Register .................................................... 155 ADCON2 Register .................................................... 155 ADRESH Register ..........................
PIC18F1220/1320 Capture/Compare/PWM (CCP) Capture Mode. See Capture. CCP1 ........................................................................ 116 CCPR1H Register ............................................ 116 CCPR1L Register ............................................ 116 Compare Mode. See Compare. Timer Resources ...................................................... 116 Clock Sources .................................................................... 15 Selection Using OSCCON Register ...........
PIC18F1220/1320 F Fail-Safe Clock Monitor .................................................... 171 Exiting Operation ..................................................... 183 Interrupts in Power Managed Modes ....................... 183 POR or Wake from Sleep ........................................ 184 WDT During Oscillator Failure ................................. 182 Fail-Safe Clock Monitor (FSCM) ...................................... 182 Fast Register Stack .............................................
PIC18F1220/1320 Internal Oscillator Block ..................................................... 14 Adjustment ................................................................. 14 INTIO Modes .............................................................. 14 INTRC Output Frequency .......................................... 14 OSCTUNE Register ................................................... 14 Internal RC Oscillator Use with WDT ..........................................................
PIC18F1220/1320 Pinout I/O Descriptions PIC18F1220/1320 ........................................................ 8 PIR Registers ..................................................................... 78 PLL Lock Time-out ............................................................. 34 Pointer, FSR ....................................................................... 53 POP .................................................................................. 220 POR. See Power-on Reset.
PIC18F1220/1320 OSCTUNE (Oscillator Tuning) ................................... 15 PIE1 (Peripheral Interrupt Enable 1) .......................... 80 PIE2 (Peripheral Interrupt Enable 2) .......................... 81 PIR1 (Peripheral Interrupt Request (Flag) 1) ............. 78 PIR2 (Peripheral Interrupt Request (Flag) 2) ............. 79 PWM1CON (PWM Configuration) ............................ 126 RCON (Reset Control) ......................................... 56, 84 RCSTA (Receive Status and Control) .....
PIC18F1220/1320 Time-out Sequence on POR w/PLL Enabled (MCLR Tied to VDD) ........................................... 40 Time-out Sequence on Power-up (MCLR Not Tied to Vdd), Case 1 ....................... 39 Time-out Sequence on Power-up (MCLR Not Tied to Vdd), Case 2 ....................... 39 Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise pwrt) ................... 39 Timer0 and Timer1 External Clock .......................... 261 Transition for Entry to SEC_IDLE Mode ....................
PIC18F1220/1320 NOTES: DS39605F-page 302 © 2007 Microchip Technology Inc.
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PIC18F1220/1320 PIC18F1220/1320 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. − PART NO. Device Device X Temperature Range /XX XXX Package Pattern PIC18F1220/1320(1), PIC18F1220/1320T(2); VDD range 4.2V to 5.5V Examples: a) b) PIC18LF1320-I/P 301 = Industrial temp., PDIP package, Extended VDD limits, QTP pattern #301. PIC18LF1220-I/SO = Industrial temp., SOIC package, Extended VDD limits.
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