Datasheet

© 2007 Microchip Technology Inc. DS39605F-page 87
PIC18F1220/1320
10.0 I/O PORTS
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction register)
• PORT register (reads the levels on the pins of the
device)
• LAT register (output latch)
The Data Latch (LATA) register is useful for read-
modify-write operations on the value that the I/O pins
are driving.
A simplified model of a generic I/O port without the
interfaces to other peripherals is shown in Figure 10-1.
FIGURE 10-1: GENERIC I/O PORT
OPERATION
10.1 PORTA, TRISA and LATA
Registers
PORTA is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
high-impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch.
The Data Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
register read and write the latched output value for
PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin.
The sixth pin of PORTA (M
CLR/VPP/RA5) is an input
only pin. Its operation is controlled by the MCLRE
configuration bit in Configuration Register 3H
(CONFIG3H<7>). When selected as a port pin
(MCLRE = 0), it functions as a digital input only pin; as
such, it does not have TRIS or LAT bits associated with
its operation. Otherwise, it functions as the device’s
Master Clear input. In either configuration, RA5 also
functions as the programming voltage input during
programming.
Pins RA6 and RA7 are multiplexed with the main oscil-
lator pins; they are enabled as oscillator or I/O pins by
the selection of the main oscillator in Configuration
Register 1H (see Section 19.1 “Configuration Bits”
for details). When they are not used as port pins, RA6
and RA7 and their associated TRIS and LAT bits are
read as ‘0’.
The other PORTA pins are multiplexed with analog
inputs, the analog V
REF+ and VREF- inputs and the LVD
input. The operation of pins RA3:RA0 as A/D converter
inputs is selected by clearing/setting the control bits in
the ADCON1 register (A/D Control Register 1).
The RA4/T0CKI pin is a Schmitt Trigger input and an
open-drain output. All other PORTA pins have TTL
input levels and full CMOS output drivers.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 10-1: INITIALIZING PORTA
Data
Bus
WR LAT
WR TRIS
RD Port
Data Latch
TRIS Latch
RD TRIS
Input
Buffer
I/O pin
(1)
QD
CK
QD
CK
EN
QD
EN
RD LAT
or Port
Note 1: I/O pins have diode protection to V
DD and VSS.
Note: On a Power-on Reset, RA5 is enabled as a
digital input only if Master Clear functionality
is disabled.
Note: On a Power-on Reset, RA3:RA0 are
configured as analog inputs and read as
‘0’. RA4 is always a digital pin.
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
CLRF LATA ; Alternate method
; to clear output
; data latches
MOVLW 0x7F ; Configure A/D
MOVWF ADCON1 ; for digital inputs
MOVLW 0xD0 ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as outputs
; RA<7:4> as inputs