Datasheet

PIC18F1220/1320
DS39605F-page 42 © 2007 Microchip Technology Inc.
5.2 Return Address Stack
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC
(Program Counter) is pushed onto the stack when a
CALL or RCALL instruction is executed, or an interrupt
is Acknowledged. The PC value is pulled off the stack
on a RETURN, RETLW or a RETFIE instruction. PCLATU
and PCLATH are not affected by any of the RETURN or
CALL instructions.
The stack operates as a 31-word by 21-bit RAM and a
5-bit stack pointer, with the Stack Pointer initialized to
00000
B after all Resets. There is no RAM associated
with Stack Pointer, 00000
B. This is only a Reset value.
During a CALL type instruction, causing a push onto the
stack, the Stack Pointer is first incremented and the
RAM location pointed to by the Stack Pointer
(STKPTR) register is written with the contents of the PC
(already pointing to the instruction following the CALL).
During a RETURN type instruction, causing a pop from
the stack, the contents of the RAM location pointed to
by the STKPTR are transferred to the PC and then the
Stack Pointer is decremented.
The stack space is not part of either program or data
space. The Stack Pointer is readable and writable and
the address on the top of the stack is readable and
writable through the top-of-stack Special File
Registers. Data can also be pushed to or popped from
the stack using the top-of-stack SFRs. Status bits
indicate if the stack is full, has overflowed or
underflowed.
5.2.1 TOP-OF-STACK ACCESS
The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL, hold the
contents of the stack location pointed to by the
STKPTR register (Figure 5-3). This allows users to
implement a software stack if necessary. After a CALL,
RCALL or interrupt, the software can read the pushed
value by reading the TOSU, TOSH and TOSL registers.
These values can be placed on a user defined software
stack. At return time, the software can replace the
TOSU, TOSH and TOSL and do a return.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
5.2.2 RETURN STACK POINTER
(STKPTR)
The STKPTR register (Register 5-1) contains the stack
pointer value, the STKFUL (Stack Full) status bit and
the STKUNF (Stack Underflow) status bits. The value
of the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. At Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System for return stack maintenance.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
The action that takes place when the stack becomes
full depends on the state of the STVR (Stack Overflow
Reset Enable) configuration bit. (Refer to Section 19.1
“Configuration Bits” for a description of the device
configuration bits.) If STVR is set (default), the 31st
push will push the (PC + 2) value onto the stack, set the
STKFUL bit and reset the device. The STKFUL bit will
remain set and the Stack Pointer will be set to zero.
If STVR is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and STKPTR will remain at 31.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or a POR occurs.
FIGURE 5-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Note: Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
00011
001A34h
11111
11110
11101
00010
00001
00000
00010
Return Address Stack
Top-of-Stack
000D58h
TOSLTOSHTOSU
34h1Ah00h
STKPTR<4:0>