Datasheet

© 2007 Microchip Technology Inc. DS39605F-page 19
PIC18F1220/1320
3.0 POWER MANAGED MODES
The PIC18F1220/1320 devices offer a total of six oper-
ating modes for more efficient power management
(see Table 3-1). These provide a variety of options for
selective power conservation in applications where
resources may be limited (i.e., battery powered
devices).
There are three categories of power managed modes:
• Sleep mode
• Idle modes
• Run modes
These categories define which portions of the device
are clocked and sometimes, what speed. The Run and
Idle modes may use any of the three available clock
sources (primary, secondary or INTOSC multiplexer);
the Sleep mode does not use a clock source.
The clock switching feature offered in other PIC18
devices (i.e., using the Timer1 oscillator in place of the
primary oscillator) and the Sleep mode offered by all
PIC
®
devices (where all system clocks are stopped) are
both offered in the PIC18F1220/1320 devices
(SEC_RUN and Sleep modes, respectively). However,
additional power managed modes are available that
allow the user greater flexibility in determining what
portions of the device are operating. The power man-
aged modes are event driven; that is, some specific
event must occur for the device to enter or (more
particularly) exit these operating modes.
For PIC18F1220/1320 devices, the power managed
modes are invoked by using the existing SLEEP
instruction. All modes exit to PRI_RUN mode when trig-
gered by an interrupt, a Reset or a WDT time-out
(PRI_RUN mode is the normal full power execution
mode; the CPU and peripherals are clocked by the pri-
mary oscillator source). In addition, power managed
Run modes may also exit to Sleep mode, or their
corresponding Idle mode.
3.1 Selecting Power Managed Modes
Selecting a power managed mode requires deciding if
the CPU is to be clocked or not and selecting a clock
source. The IDLEN bit controls CPU clocking, while the
SCS1:SCS0 bits select a clock source. The individual
modes, bit settings, clock sources and affected
modules are summarized in Table 3-1.
3.1.1 CLOCK SOURCES
The clock source is selected by setting the SCS bits of
the OSCCON register (Register 2-2). Three clock
sources are available for use in power managed Idle
modes: the primary clock (as configured in Configuration
Register 1H), the secondary clock (Timer1 oscillator)
and the internal oscillator block. The secondary and
internal oscillator block sources are available for the
power managed modes (PRI_RUN mode is the normal
full power execution mode; the CPU and peripherals are
clocked by the primary oscillator source).
TABLE 3-1: POWER MANAGED MODES
Mode
OSCCON Bits Module Clocking
Available Clock and Oscillator Source
IDLEN
<7>
SCS1:SCS0
<1:0>
CPU Peripherals
Sleep 000 Off Off None – All clocks are disabled
PRI_RUN 000Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC, INTRC
(1)
This is the normal full power execution mode.
SEC_RUN 001Clocked Clocked Secondary – Timer1 Oscillator
RC_RUN 01xClocked Clocked Internal Oscillator Block
(1)
PRI_IDLE 100 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC
SEC_IDLE 101 Off Clocked Secondary – Timer1 Oscillator
RC_IDLE 11x Off Clocked Internal Oscillator Block
(1)
Note 1: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.