Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller PDIP 18 8-Bit 40 MHz I/O number 16

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Table Of Contents

Low-Power Features:
Oscillators:
Peripheral Highlights:
Special Microcontroller Features:
Pin Diagrams
Table of Contents
Most Current Data Sheet
Errata
Customer Notification System
1.0 Device Overview
- 1.1 New Core Features
  - 1.1.1 Nanowatt Technology
  - 1.1.2 Multiple Oscillator Options and Features
- 1.2 Other Special Features
- 1.3 Details on Individual Family Members
2.0 Oscillator Configurations
- 2.1 Oscillator Types
- 2.2 Crystal Oscillator/Ceramic Resonators
- 2.3 HSPLL
  - FIGURE 2-3: PLL Block Diagram
- 2.4 External Clock Input
  - FIGURE 2-4: External Clock Input Operation (EC Configuration)
  - FIGURE 2-5: External Clock Input Operation (ECIO Configuration)
- 2.5 RC Oscillator
  - FIGURE 2-6: RC Oscillator Mode
  - FIGURE 2-7: RCIO Oscillator Mode
- 2.6 Internal Oscillator Block
- 2.7 Clock Sources and Oscillator Switching
  - 2.7.1 Oscillator Control Register
    - FIGURE 2-8: PIC18F1220/1320 Clock Diagram
    - Register 2-2: OSCCON Register
  - 2.7.2 Oscillator Transitions
- 2.8 Effects of Power Managed Modes on the Various Clock Sources
- 2.9 Power-up Delays
  - TABLE 2-3: OSC1 and OSC2 Pin States in Sleep Mode
3.0 Power Managed Modes
- 3.1 Selecting Power Managed Modes
- 3.2 Sleep Mode
- 3.3 Idle Modes
- 3.4 Run Modes
- 3.5 Wake from Power Managed Modes
- 3.6 INTOSC Frequency Drift
4.0 Reset
- FIGURE 4-1: Simplified Block Diagram of On-Chip Reset Circuit
- 4.1 Power-on Reset (POR)
  - FIGURE 4-2: External Power-on Reset Circuit (for Slow Vdd Power-up)
- 4.2 Power-up Timer (PWRT)
- 4.3 Oscillator Start-up Timer (OST)
- 4.4 PLL Lock Time-out
- 4.5 Brown-out Reset (BOR)
- 4.6 Time-out Sequence
5.0 Memory Organization
- FIGURE 5-1: Program Memory Map and Stack for PIC18F1220
- 5.1 Program Memory Organization
  - FIGURE 5-2: Program Memory Map and Stack for PIC18F1320
- 5.2 Return Address Stack
- 5.3 Fast Register Stack
  - EXAMPLE 5-1: Fast Register Stack Code Example
- 5.4 PCL, PCLATH and PCLATU
- 5.5 Clocking Scheme/Instruction Cycle
- 5.6 Instruction Flow/Pipelining
  - FIGURE 5-4: Clock/Instruction Cycle
  - EXAMPLE 5-2: Instruction Pipeline Flow
- 5.7 Instructions in Program Memory
  - FIGURE 5-5: Instructions in Program Memory
  - 5.7.1 Two-Word Instructions
    - EXAMPLE 5-3: Two-Word Instructions
- 5.8 Look-up Tables
  - 5.8.1 Computed GOTO
    - EXAMPLE 5-4: Computed GOTO Using an Offset Value
  - 5.8.2 Table Reads/Table Writes
- 5.9 Data Memory Organization
  - 5.9.1 General Purpose Register File
    - FIGURE 5-6: Data Memory Map for PIC18F1220/1320 Devices
  - 5.9.2 Special Function Registers
    - TABLE 5-1: Special Function Register Map for PIC18F1220/1320 Devices
    - TABLE 5-2: Register File Summary (PIC18F1220/1320)
- 5.10 Access Bank
- 5.11 Bank Select Register (BSR)
  - FIGURE 5-7: Direct Addressing
- 5.12 Indirect Addressing, INDF and FSR Registers
  - EXAMPLE 5-5: How to Clear RAM (Bank 1) Using Indirect Addressing
  - 5.12.1 Indirect Addressing Operation
    - FIGURE 5-8: Indirect Addressing Operation
    - FIGURE 5-9: Indirect Addressing
- 5.13 Status Register
  - Register 5-2: Status Register
- 5.14 RCON Register
  - Register 5-3: RCON Register
6.0 Flash Program Memory
- 6.1 Table Reads and Table Writes
  - FIGURE 6-1: Table Read Operation
  - FIGURE 6-2: Table Write Operation
- 6.2 Control Registers
- 6.3 Reading the Flash Program Memory
  - FIGURE 6-4: Reads from Flash Program Memory
  - EXAMPLE 6-1: Reading a Flash Program Memory Word
- 6.4 Erasing Flash Program Memory
  - 6.4.1 Flash Program Memory Erase Sequence
    - EXAMPLE 6-2: Erasing a Flash Program Memory Row
- 6.5 Writing to Flash Program Memory
- 6.6 Flash Program Operation During Code Protection
  - TABLE 6-2: Registers Associated with Program Flash Memory
7.0 Data EEPROM Memory
- 7.1 EEADR
- 7.2 EECON1 and EECON2 Registers
  - Register 7-1: EECON1 Register
- 7.3 Reading the Data EEPROM Memory
- 7.4 Writing to the Data EEPROM Memory
- 7.5 Write Verify
- 7.6 Protection Against Spurious Write
  - EXAMPLE 7-1: Data EEPROM Read
  - EXAMPLE 7-2: Data EEPROM Write
- 7.7 Operation During Code-Protect
- 7.8 Using the Data EEPROM
  - EXAMPLE 7-3: Data EEPROM Refresh Routine
  - TABLE 7-1: Registers Associated with Data EEPROM Memory
8.0 8 X 8 Hardware Multiplier
- 8.1 Introduction
  - TABLE 8-1: Performance Comparison
- 8.2 Operation
9.0 Interrupts
- FIGURE 9-1: Interrupt Logic
- 9.1 INTCON Registers
- 9.2 PIR Registers
  - Register 9-4: PIR1: Peripheral Interrupt Request (Flag) Register 1
  - Register 9-5: PIR2: Peripheral Interrupt Request (Flag) Register 2
- 9.3 PIE Registers
  - Register 9-6: PIE1: Peripheral Interrupt Enable Register 1
  - Register 9-7: PIE2: Peripheral Interrupt Enable Register 2
- 9.4 IPR Registers
  - Register 9-8: IPR1: Peripheral Interrupt Priority Register 1
  - Register 9-9: IPR2: Peripheral Interrupt Priority Register 2
- 9.5 RCON Register
  - Register 9-10: RCON Register
- 9.6 INTn Pin Interrupts
- 9.7 TMR0 Interrupt
- 9.8 PORTB Interrupt-on-Change
- 9.9 Context Saving During Interrupts
  - EXAMPLE 9-1: Saving Status, WREG and BSR Registers in RAM
10.0 I/O Ports
- FIGURE 10-1: Generic I/O Port Operation
- 10.1 PORTA, TRISA and LATA Registers
- 10.2 PORTB, TRISB and LATB Registers
11.0 Timer0 Module
- Register 11-1: T0CON: Timer0 Control Register
- FIGURE 11-1: Timer0 Block Diagram in 8-Bit Mode
- FIGURE 11-2: Timer0 Block Diagram in 16-Bit Mode
- 11.1 Timer0 Operation
- 11.2 Prescaler
  - 11.2.1 Switching Prescaler Assignment
- 11.3 Timer0 Interrupt
- 11.4 16-Bit Mode Timer Reads and Writes
  - TABLE 11-1: Registers Associated with Timer0
12.0 Timer1 Module
- Register 12-1: T1CON: Timer1 Control Register
- 12.1 Timer1 Operation
  - FIGURE 12-1: Timer1 Block Diagram
  - FIGURE 12-2: Timer1 Block Diagram: 16-Bit Read/Write Mode
- 12.2 Timer1 Oscillator
  - FIGURE 12-3: External Components for the Timer1 LP Oscillator
  - TABLE 12-1: Capacitor Selection for the Timer Oscillator
- 12.3 Timer1 Oscillator Layout Considerations
  - FIGURE 12-4: Oscillator Circuit with Grounded Guard Ring
- 12.4 Timer1 Interrupt
- 12.5 Resetting Timer1 Using a CCP Trigger Output
- 12.6 Timer1 16-Bit Read/Write Mode
- 12.7 Using Timer1 as a Real-Time Clock
  - EXAMPLE 12-1: Implementing a Real-Time Clock Using a Timer1 Interrupt Service
  - TABLE 12-2: Registers Associated with Timer1 as a Timer/Counter
13.0 Timer2 Module
- 13.1 Timer2 Operation
  - Register 13-1: T2CON: Timer2 Control Register
- 13.2 Timer2 Interrupt
- 13.3 Output of TMR2
  - FIGURE 13-1: Timer2 Block Diagram
  - TABLE 13-1: Registers Associated with Timer2 as a Timer/Counter
14.0 Timer3 Module
- Register 14-1: T3CON: Timer3 Control Register
- 14.1 Timer3 Operation
  - FIGURE 14-1: Timer3 Block Diagram
  - FIGURE 14-2: Timer3 Block Diagram Configured in 16-Bit Read/Write Mode
- 14.2 Timer1 Oscillator
- 14.3 Timer3 Interrupt
- 14.4 Resetting Timer3 Using a CCP Trigger Output
  - TABLE 14-1: Registers Associated with Timer3 as a Timer/Counter
15.0 Enhanced Capture/ Compare/PWM (ECCP) Module
- Register 15-1: CCP1CON Register for Enhanced CCP Operation
- 15.1 ECCP Outputs
  - TABLE 15-1: Pin Assignments for Various ECCP Modes
- 15.2 CCP Module
  - TABLE 15-2: CCP Mode – Timer Resource
- 15.3 Capture Mode
- 15.4 Compare Mode
- 15.5 Enhanced PWM Mode
16.0 Enhanced Addressable Universal Synchronous Asynchronous Receiver Transmitter (EUSART)
- 16.1 Asynchronous Operation in Power Managed Modes
- 16.2 EUSART Baud Rate Generator (BRG)
- 16.3 EUSART Asynchronous Mode
- 16.4 EUSART Synchronous Master Mode
  - 16.4.1 EUSART Synchronous Master Transmission
  - 16.4.2 EUSART Synchronous Master Reception
    - FIGURE 16-12: Synchronous Reception (Master Mode, SREN)
    - TABLE 16-8: Registers Associated with Synchronous Master Reception
- 16.5 EUSART Synchronous Slave Mode
  - 16.5.1 EUSART Synchronous Slave Transmit
    - TABLE 16-9: Registers Associated with Synchronous Slave Transmission
  - 16.5.2 EUSART Synchronous Slave Reception
    - TABLE 16-10: Registers Associated with Synchronous Slave Reception
17.0 10-Bit Analog-to-Digital Converter (A/D) Module
- Register 17-1: ADCON0: A/D Control Register 0
- Register 17-2: ADCON1: A/D Control Register 1
- Register 17-3: ADCON2: A/D Control Register 2
- FIGURE 17-1: A/D Block Diagram
- FIGURE 17-2: Analog Input Model
- 17.1 A/D Acquisition Requirements
- 17.2 A/D Vref+ and Vref- References
- 17.3 Selecting and Configuring Automatic Acquisition Time
- 17.4 Selecting the A/D Conversion Clock
  - TABLE 17-1: Tad vs. Device Operating Frequencies
- 17.5 Operation in Low-Power Modes
- 17.6 Configuring Analog Port Pins
- 17.7 A/D Conversions
  - FIGURE 17-3: A/D Conversion Tad Cycles (Acqt<2:0> = 000, Tacq = 0)
  - FIGURE 17-4: A/D Conversion Tad Cycles (Acqt<2:0> = 010, Tacq = 4 Tad)
- 17.8 Use of the CCP1 Trigger
  - TABLE 17-2: Summary of A/D Registers
18.0 Low-Voltage Detect
- FIGURE 18-1: Typical Low-Voltage Detect Application
- FIGURE 18-2: Low-Voltage Detect (LVD) Block Diagram
- FIGURE 18-3: Low-Voltage Detect (LVD) with External Input Block Diagram
- 18.1 Control Register
  - Register 18-1: LVDCON Register
- 18.2 Operation
- 18.3 Operation During Sleep
- 18.4 Effects of a Reset
19.0 Special Features of the CPU
- 19.1 Configuration Bits
- 19.2 Watchdog Timer (WDT)
  - 19.2.1 Control Register
- 19.3 Two-Speed Start-up
  - 19.3.1 Special Considerations for Using Two-Speed Start-up
    - FIGURE 19-2: Timing Transition for Two-Speed Start-up (INTOSC to HSPLL)
- 19.4 Fail-Safe Clock Monitor
- 19.5 Program Verification and Code Protection
- 19.6 ID Locations
- 19.7 In-Circuit Serial Programming
  - TABLE 19-4: ICSP/ICD Connections
- 19.8 In-Circuit Debugger
  - TABLE 19-5: Debugger Resources
- 19.9 Low-Voltage ICSP Programming
20.0 Instruction Set Summary
- 20.1 ReadModify-Write Operations
- 20.2 Instruction Set
21.0 Development Support
- 21.1 MPLAB Integrated Development Environment Software
- 21.2 MPASM Assembler
- 21.3 MPLAB C18 and MPLAB C30 C Compilers
- 21.4 MPLINK Object Linker/ MPLIB Object Librarian
- 21.5 MPLAB ASM30 Assembler, Linker and Librarian
- 21.6 MPLAB SIM Software Simulator
- 21.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator
- 21.8 MPLAB REAL ICE In-Circuit Emulator System
- 21.9 MPLAB ICD 2 In-Circuit Debugger
- 21.10 MPLAB PM3 Device Programmer
- 21.11 PICSTART Plus Development Programmer
- 21.12 PICkit 2 Development Programmer
- 21.13 Demonstration, Development and Evaluation Boards
22.0 Electrical Characteristics
- Absolute Maximum Ratings(†)
- 22.1 DC Characteristics: Supply Voltage PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial)
- 22.2 DC Characteristics: Power-Down and Supply Current PIC18F1220/1320 (Industrial) PIC18LF1220/1...
- 22.3 DC Characteristics: PIC18F1220/1320 (Industrial) PIC18LF1220/1320 (Industrial)
- 22.4 AC (Timing) Characteristics
23.0 DC and AC Characteristics Graphs and Tables
- FIGURE 23-1: Typical Idd vs. Fosc Over Vdd PRI_RUN, EC Mode, +25˚C
- FIGURE 23-2: Maximum Idd vs. Fosc Over Vdd PRI_RUN, EC Mode, -40˚C to +85˚C
- FIGURE 23-3: Maximum Idd vs. Fosc Over Vdd PRI_RUN, EC Mode, -40˚C to +125˚C
- FIGURE 23-4: Typical Idd vs. Fosc Over Vdd PRI_RUN, EC Mode, +25˚C
- FIGURE 23-5: Maximum Idd vs. Fosc Over Vdd PRI_RUN, EC Mode, -40˚C to +125˚C
- FIGURE 23-6: Typical Idd vs. Fosc Over Vdd PRI_RUN, EC Mode, +25˚C
- FIGURE 23-7: Maximum Idd vs. Fosc Over Vdd PRI_RUN, EC Mode, -40˚C to +125˚C
- FIGURE 23-8: Typical Idd vs. Fosc Over Vdd PRI_IDLE, EC Mode, +25˚C
- FIGURE 23-9: Maximum Idd vs. Fosc Over Vdd PRI_IDLE, EC Mode, -40˚C to +85˚C
- FIGURE 23-10: Maximum Idd vs. Fosc Over Vdd PRI_IDLE, EC Mode, -40˚C to +125˚C
- FIGURE 23-11: Typical Idd vs. Fosc Over Vdd PRI_IDLE, EC Mode, +25˚C
- FIGURE 23-12: Maximum Idd vs. Fosc Over Vdd PRI_IDLE, EC Mode, -40˚C to +125˚C
- FIGURE 23-13: Typical Idd vs. Fosc Over Vdd PRI_IDLE, EC Mode, +25˚C
- FIGURE 23-14: Maximum Idd vs. Fosc Over Vdd PRI_IDLE, EC Mode, -40˚C to +125˚C
- FIGURE 23-15: Typical Ipd vs. Vdd (+25˚C), 125 kHz to 8 MHz RC_RUN Mode, All Peripherals Disabled
- FIGURE 23-16: Maximum Ipd vs. Vdd (-40˚C to +125˚C), 125 kHz to 8 MHz RC_RUN Mode, All Peripheral...
- FIGURE 23-17: Typical and Maximum Ipd vs. Vdd (-40˚C to +125˚C), 31.25 kHz RC_RUN Mode, All Perip...
- FIGURE 23-18: Typical Ipd vs. Vdd (+25˚C), 125 kHz to 8 MHz RC_IDLE Mode, All Peripherals Disabled
- FIGURE 23-19: Maximum Ipd vs. Vdd (-40˚C to +125˚C), 125 kHz to 8 MHz RC_IDLE Mode, All Periphera...
- FIGURE 23-20: Typical and Maximum Ipd vs. Vdd (-40˚C to +125˚C), 31.25 kHz RC_IDLE Mode, All Peri...
- FIGURE 23-21: Ipd SEC_RUN Mode, -10˚C to +70˚C, 32.768 kHz XTAL, 2 x 22 pF, All Peripherals Disabled
- FIGURE 23-22: Ipd SEC_IDLE Mode, -10˚C to +70˚C, 32.768 kHz, 2 x 22 pF, All Peripherals Disabled
- FIGURE 23-23: Total Ipd, -40˚C to +125˚C Sleep Mode, All Peripherals Disabled
- FIGURE 23-24: Voh vs. Ioh Over Temperature (-40˚C to +125˚C), Vdd = 3.0V
- FIGURE 23-25: Voh vs. Ioh Over Temperature (-40˚C to +125˚C), Vdd = 5.0V
- FIGURE 23-26: Vol vs. Iol Over Temperature (-40˚C to +125˚C), Vdd = 3.0V
- FIGURE 23-27: Vol vs. Iol Over Temperature (-40˚C to +125˚C), Vdd = 5.0V
- FIGURE 23-28: DIpd Timer1 Oscillator, -10˚C to +70˚C Sleep Mode, TMR1 Counter Disabled
- FIGURE 23-29: DIpd FSCM vs. Vdd Over Temperature PRI_IDLE Mode, EC Oscillator at 32 kHz, -40˚C to...
- FIGURE 23-30: DIpd WDT, -40˚C to +125˚C Sleep Mode, All Peripherals Disabled
- FIGURE 23-31: DIpd LVD vs. Vdd Sleep Mode, LVDL3:LVDL0 = 0001 (2V)
- FIGURE 23-32: DIpd BOR vs. Vdd, -40˚C to +125˚C Sleep Mode, BORV1:BORV0 = 11 (2V)
- FIGURE 23-33: DIpd A/D, -40˚C to +125˚C Sleep Mode, A/D Enabled (Not Converting)
- FIGURE 23-34: Average Fosc vs. Vdd for Various R’s External RC Mode, C = 20 pF, Temperature = +25˚C
- FIGURE 23-35: Average Fosc vs. Vdd for Various R’s External RC Mode, C = 100 pF, Temperature = +25˚C
- FIGURE 23-36: Average Fosc vs. Vdd for Various R’s External RC Mode, C = 300 pF, Temperature = +25˚C
24.0 Packaging Information
- 24.1 Package Marking Information
- 24.2 Package Details
Appendix A: Revision History
- Revision A (August 2002)
- Revision B (November 2002)
- Revision C (May 2004)
- Revision D (October 2006)
- Revision E (January 2007)
- Revision F (February 2007)
Appendix B: Device Differences
- TABLE B-1: Device Differences
Appendix C: Conversion Considerations
Appendix D: Migration from Baseline to Enhanced Devices
Appendix E: Migration from Mid-Range to Enhanced Devices
Appendix F: Migration from High-End to Enhanced Devices
INDEX
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PIC18F1220/1320

BRA Unconditional Branch

Syntax: [ label ] BRA n

Operands: -1024 ≤ n ≤ 1023

Operation: (PC) + 2 + 2n → PC

Status Affected: None

Encoding:

1101 0nnn nnnn nnnn

Description: Add the 2’s complement number

‘2n’ to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is a

two-cycle instruction.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

Write to PC

operation

Example:

HERE BRA Jump

Before Instruction

PC = address (HERE)

After Instruction

PC = address (Jump)

BSF Bit Set f

Syntax: [ label ] BSF f,b[,a]

Operands: 0 ≤ f ≤ 255

0 ≤ b ≤ 7

a ∈ [0,1]

Operation: 1 → f<b>

Status Affected: None

Encoding:

1000 bbba ffff ffff

Description: Bit ‘b’ in register ‘f’ is set. If ‘a’ is ‘0’,

the Access Bank will be selected,

overriding the BSR value. If ‘a’ = 1,

then the bank will be selected as

per the BSR value.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write

Example:

BSF FLAG_REG, 7

Before Instruction

FLAG_REG = 0x0A

After Instruction

FLAG_REG = 0x8A