Datasheet

PIC18F1230/1330
 2009 Microchip Technology Inc. DS39758D-page 89
TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
PORTA RA7
(1)
RA6
(1)
RA5 RA4 RA3 RA2 RA1 RA0 50
LATA LATA7
(1)
LATA6
(1)
PORTA Output Latch Register (Read and Write to Data Latch) 49
TRISA TRISA7
(1)
TRISA6
(1)
PORTA Data Direction Control Register 49
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47
INTCON2
RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 47
ADCON1
— — — VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 48
CMCON C2OUT C1OUT C0OUT — — CMEN2 CMEN1 CMEN0 48
CVRCON CVREN — CVRR CVRSS CVR3 CVR2 CVR1 CVR0 48
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator
configuration; otherwise, they are read as ‘0’.