Datasheet

PIC18F1230/1330
DS39758D-page 62  2009 Microchip Technology Inc.
STATUS — — —NOVZ DC C---x xxxx 48, 64
TMR0H Timer0 Register High Byte 0000 0000 48, 109
TMR0L Timer0 Register Low Byte xxxx xxxx 48, 109
T0CON TMR0ON T016BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 48, 107
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0100 q000 48, 28
LVDCON
— — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 48, 187
WDTCON
— — — — — — —SWDTEN
(7)
---- ---0 48, 203
RCON IPEN SBOREN
(1)
—RITO PD POR BOR 0q-1 11q0 48, 40
TMR1H Timer1 Register High Byte xxxx xxxx 48, 115
TMR1L Timer1 Register Low Byte xxxx xxxx 48, 115
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 0000 0000 48, 111
ADRESH A/D Result Register High Byte xxxx xxxx 48, 178
ADRESL A/D Result Register Low Byte xxxx xxxx 48, 178
ADCON0 SEVTEN
— — — CHS1 CHS0 GO/DONE ADON 0--- 0000 48, 169
ADCON1
— — — VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 ---0 1111 48, 170
ADCON2 ADFM
— ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 48, 171
BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16
— WUE ABDEN 01-0 00-00 48, 150
CVRCON CVREN
— CVRR CVRSS CVR3 CVR2 CVR1 CVR0 0-00 0000 48, 184
CMCON C2OUT C1OUT C0OUT
— — CMEN2 CMEN1 CMEN0 000- -000 48, 179
SPBRGH EUSART Baud Rate Generator Register High Byte 0000 0000 48, 152
SPBRG EUSART Baud Rate Generator Register Low Byte 0000 0000 48, 152
RCREG EUSART Receive Register 0000 0000 48, 160
TXREG EUSART Transmit Register 0000 0000 48, 157
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 48, 148
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 48, 149
EEADR EEPROM Address Register 0000 0000 49, 81
EEDATA EEPROM Data Register 0000 0000 49, 81
EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 49, 72
EECON1 EEPGD CFGS
— FREE WRERR WREN WR RD xx-0 x000 48, 73
IPR3
— — —PTIP— — — — ---1 ---- 49, 103
PIR3
— — —PTIF— — — — ---0 ---- 49, 99
PIE3
— — —PTIE— — — — ---0 ---- 49, 101
IPR2 OSCFIP
— — EEIP —LVDIP — — 1--1 -1-- 49, 103
PIR2 OSCFIF
— —EEIF—LVDIF — — 0--0 -0-- 49, 99
PIE2 OSCFIE
— — EEIE —LVDIE — — 0--0 -0-- 49, 101
IPR1
— ADIP RCIP TXIP CMP2IP CMP1IP CMP0IP TMR1IP -111 1111 49, 102
PIR1
— ADIF RCIF TXIF CMP2IF CMP1IF CMP0IF TMR1IF -000 0000 49, 98
PIE1
— ADIE RCIE TXIE CMP2IE CMP1IE CMP0IE TMR1IE -000 0000 49, 100
OSCTUNE INTSRC PLLEN
(2)
— TUN4 TUN3 TUN2 TUN1 TUN0 00-0 0000 49, 25
PTCON0 PTOPS3 PTOPS2 PTOPS1 PTOPS0 PTCKPS1 PTCKPS0 PTMOD1 PTMOD0 0000 0000 49, 122
PTCON1 PTEN PTDIR
— — — — — — 00-- ---- 49, 122
TABLE 6-2: REGISTER FILE SUMMARY (PIC18F1230/1330) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Details
on
Page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads
as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”.
2: The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See
Section 3.6.4 “PLL in INTOSC Modes”.
3: The RA5 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RA5 reads as
‘0’. This bit is read-only.
4: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
5: Bit 7 and bit 6 are cleared by user software or by a POR.
6: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L.
7: This bit has no effect if the Configuration bit, WDTEN, is enabled.