Datasheet
PIC18F1230/1330
2009 Microchip Technology Inc. DS39758D-page 49
EEADR 1230 1330 0000 0000 0000 0000 uuuu uuuu
EEDATA 1230 1330 0000 0000 0000 0000 uuuu uuuu
EECON2 1230 1330 0000 0000 0000 0000 0000 0000
EECON1 1230 1330 xx-0 x000 uu-0 u000 uu-0 u000
IPR3 1230 1330 ---1 ---- ---1 ---- ---u ----
PIR3 1230 1330 ---0 ---- ---0 ---- ---u ----
PIE3 1230 1330 ---0 ---- ---0 ---- ---u ----
IPIR2 1230 1330 1--1 -1-- 1--1 -1-- u--u -u--
PIR2 1230 1330 0--0 -0-- 0--0 -0-- u--u -u--
(1)
PIE2 1230 1330 0--0 -0-- 0--0 -0-- u--u -u--
IPR1 1230 1330 -111 1111 -111 1111 -uuu uuuu
PIR1 1230 1330 -000 0000 -000 0000 -uuu uuuu
(1)
PIE1 1230 1330 -000 0000 -000 0000 -uuu uuuu
OSCTUNE 1230 1330 00-0 0000 00-0 0000 uu-u uuuu
PTCON0 1230 1330 0000 0000 uuuu uuuu uuuu uuuu
PTCON1 1230 1330 00-- ---- 00-- ---- uu-- ----
PTMRL 1230 1330 0000 0000 0000 0000 uuuu uuuu
PTMRH 1230 1330 ---- 0000 ---- 0000 ---- uuuu
PTPERL 1230 1330 1111 1111 1111 1111 uuuu uuuu
PTPERH 1230 1330 ---- 1111 ---- 1111 ---- uuuu
TRISB 1230 1330 1111 1111 1111 1111 uuuu uuuu
TRISA 1230 1330 1111 1111
(5)
1111 1111
(5)
uuuu uuuu
(5)
PDC0L 1230 1330 0000 0000 0000 0000 uuuu uuuu
PDC0H 1230 1330 --00 0000 --00 0000 --uu uuuu
PDC1L 1230 1330 0000 0000 0000 0000 uuuu uuuu
PDC1H 1230 1330 --00 0000 --00 0000 --uu uuuu
PDC2L 1230 1330 0000 0000 0000 0000 uuuu uuuu
PDC2H 1230 1330 --00 0000 --00 0000 --uu uuuu
FLTCONFIG 1230 1330 0--- -000 0--- -000 u--- -uuu
LATB 1230 1330 xxxx xxxx uuuu uuuu uuuu uuuu
LATA 1230 1330 xxxx xxxx
(5)
uuuu uuuu
(5)
uuuu uuuu
(5)
SEVTCMPL 1230 1330 0000 0000 0000 0000 uuuu uuuu
TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable
Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 5-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read as ‘0’.
6: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L.