Datasheet

PIC18F1230/1330
DS39758D-page 182  2009 Microchip Technology Inc.
TABLE 17-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on Page:
CMCON C2OUT C1OUT C0OUT — — CMEN2 CMEN1 CMEN0 48
CVRCON CVREN
—CVRRCVRSS CVR3 CVR2 CVR1 CVR0 48
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 47
PIR1 — ADIF RCIF TXIF CMP2IF CMP1IF CMP0IF TMR1IF 49
PIE1
— ADIE RCIE TXIE CMP2IE CMP1IE CMP0IE TMR1IE 49
IPR1 — ADIP RCIP TXIP CMP2IP CMP1IP CMP0IP TMR1IP 49
PORTA RA7
(1)
RA6
(1)
RA5
(2)
RA4 RA3 RA2 RA1 RA0 50
LATA LATA7
(1)
LATA6
(1)
PORTA Data Latch Register (Read and Write to Data Latch) 49
TRISA TRISA7
(1)
TRISA6
(1)
PORTA Data Direction Control Register 49
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 50
LATB PORTB Data Latch Register (Read and Write to Data Latch) 49
TRISB PORTB Data Direction Control Register 49
Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.
Note 1: PORTA<7:6> and their direction and latch bits are individually configured as port pins based on various
primary oscillator modes. When disabled, these bits read as ‘0’.
2: The RA5 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0);
otherwise, RA5 reads as ‘0’. This bit is read-only.