Datasheet

PIC18F1230/1330
DS39758D-page 124  2009 Microchip Technology Inc.
REGISTER 14-4: PWMCON1: PWM CONTROL REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0 SEVTDIR — UDIS OSYNC
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 SEVOPS3:SEVOPS0: PWM Special Event Trigger Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
.
.
.
1111 = 1:16 Postscale
bit 3 SEVTDIR: Special Event Trigger Time Base Direction bit
1 = A Special Event Trigger will occur when the PWM time base is counting downwards
0 = A Special Event Trigger will occur when the PWM time base is counting upwards
bit 2 Unimplemented: Read as ‘0’
bit 1 UDIS: PWM Update Disable bit
1 = Updates from Duty Cycle and Period Buffer registers are disabled
0 = Updates from Duty Cycle and Period Buffer registers are enabled
bit 0 OSYNC: PWM Output Override Synchronization bit
1 = Output overrides via the OVDCON register are synchronized to the PWM time base
0 = Output overrides via the OVDCON register are asynchronous