Datasheet

PIC18F1230/1330

DS39758D-page 102  2009 Microchip Technology Inc.

11.4 IPR Registers

The IPR registers contain the individual priority bits for

the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are three Peripheral

Interrupt Priority registers (IPR1, IPR2 and IPR3). Using

the priority bits requires that the Interrupt Priority Enable

(IPEN) bit be set.

U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

— ADIP RCIP TXIP CMP2IP CMP1IP CMP0IP TMR1IP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 ADIP: A/D Converter Interrupt Priority bit

1 = High priority

0 = Low priority

bit 5 RCIP: EUSART Receive Interrupt Priority bit

1 = High priority

0 = Low priority

bit 4 TXIP: EUSART Transmit Interrupt Priority bit

1 = High priority

0 = Low priority

bit 3 CMP2IP: Analog Comparator 2 Interrupt Priority bit

1 = CMP2 is high priority

0 = CMP2 is low priority

bit 2 CMP1IP: Analog Comparator 1 Interrupt Priority bit

1 = CMP1 is high priority

0 = CMP1 is low priority

bit 1 CMP0IP: Analog Comparator 0 Interrupt Priority bit

1 = CMP0 is high priority

0 = CMP0 is low priority

bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit

1 = High priority

0 = Low priority