Information

PIC18F1230/1330
DS80308D-page 2 © 2008 Microchip Technology Inc.
4. Module: Comparator Voltage Reference
The comparator voltage reference module
(CV
REF) does not offer the option of bypassing the
CV
REF module.
The CV
REF module offers the option of providing
the following inputs to the comparators:
•Scaled V
DD
•Scaled VREF
• No reference (disabled)
Table 1 shows how the CVREN and CVRSS bits
are configured to enable the options.
5. Module: Enhanced Universal
Synchronous Asynchronous
Receiver Transmitter (EUSART)
In rare situations when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (the SPEN bit,
RCSTA <7> = 0)
• The EUSART is re-enabled (RCSTA <7> = 1)
• A two-cycle instruction is executed
Work around
Add a 2 TCY delay after re-enabling the EUSART.
1. Disable Receive Interrupts (RCIE bit,
PIE1<5> = 0).
2. Disable the EUSART (RCSTA <7> = 0).
3. Re-enable the EUSART (RCSTA <7> = 1).
4. Re-enable receive interrupts (PIE1<5> = 1).
(This is the first TCY delay.)
5. Execute a NOP instruction.
(This is the second T
CY delay.)
Date Codes that pertain to this issue:
All engineering and production devices.
TABLE 1: VOLTAGE REFERENCE
OUTPUT
CVREN
CVRCON<7>
CVRSS
CVRCON<4>
Comparator
Reference
0x (don’t care) Disabled
10CV
REF uses AVDD
11CVREF uses VREF