Information

PIC18F1230/1330
DS80352B-page 2 © 2008 Microchip Technology Inc.
3. Module: Enhanced Universal
Synchronous Receiver
Transmitter (EUSART)
The BAUDCON register is changed to add one bit
and rename another:
• Added bit – Bit 5, previously unimplemented, is
now RXDTP
• Renamed bit – Bit 4, previously SCKP, is now
TXCKP
The TXCKP and RXDTP bits allow the Asynchro-
nous mode TX and RX signals to be inverted
(polarity reversed). RXDTP has no effect on the
Synchronous mode DT signal.
The register table and new bit descriptions appear
as shown.
REGISTER 14-3: BAUDCON: BAUD RATE CONTROL REGISTER
R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 5 RXDTP: Received Data Polarity Select bit
Asynchronous mode:
1 = RX data is inverted
0 = RX data is not inverted
Synchronous mode:
Unused in this mode
bit 4 TXCKP: Clock and Data Polarity Select bit
Asynchronous mode:
1 = TX data is inverted
0 = TX data is not inverted
Synchronous mode:
1 = CK clocks are inverted
0 = CK clocks are not inverted