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PIC18F1230/1330

Clarifications/Corrections to the Data

Sheet:

In the Device Data Sheet (DS39758C), the following

clarifications and corrections should be noted. Any

silicon issues related to the PIC18F1230/1330 will be

reported in a separate silicon errata. Please check the

Microchip web site for any existing issues.

1. Module: Oscillator Configurations – PLL

The second paragraph of Section 2.6.4 “PLL in

INTOSC Modes”, is modified by the addition of

new text shown in bold.

Unlike HSPLL mode, the PLL is controlled through

software. The control bit, PLLEN (OSCTUNE<6>), is

used to enable or disable its operation. If PLL is

enabled and a Two-Speed Start-up from wake is

performed, execution is delayed until the PLL

starts.

2. Module: Flash Program Memory

In Section 6.2.4 “Table Pointer Boundaries”,

the third paragraph and Figure 6-3 are modified:

• The paragraph is modified by the removal of the

first sentence and the addition of new text

shown in bold.

When the timed write to program memory begins (via

the WR bit), the 19 MSbs of the TBLPTR

(TBLPTR<21:3>) determine which program memory

block of 8 bytes is written to. The Table Pointer

For more detail, see Section 6.5 “Writing to Flash

Program Memory”.

• Figure 6-3 is modified as shown.

FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION

21 16 15 87 0

TABLE ERASE

TABLE WRITE

TABLE READ – TBLPTR<21:0>

TBLPTRL

TBLPTRH

TBLPTRU

TBLPTR<21:3>

TBLPTR<21:6>

PIC18F1230/1330 Data Sheet Errata

Summary of content (12 pages)

PAGE 1
PIC18F1230/1330 PIC18F1230/1330 Data Sheet Errata 2. Module: Flash Program Memory Clarifications/Corrections to the Data Sheet: In the Device Data Sheet (DS39758C), the following clarifications and corrections should be noted. Any silicon issues related to the PIC18F1230/1330 will be reported in a separate silicon errata. Please check the Microchip web site for any existing issues. 1. Module: Oscillator Configurations – PLL The second paragraph of Section 2.6.
PAGE 2
PIC18F1230/1330 3. Module: Enhanced Universal Synchronous Receiver Transmitter (EUSART) The TXCKP and RXDTP bits allow the Asynchronous mode TX and RX signals to be inverted (polarity reversed). RXDTP has no effect on the Synchronous mode DT signal. The BAUDCON register is changed to add one bit and rename another: The register table and new bit descriptions appear as shown.
PAGE 3
PIC18F1230/1330 4. Module: 10-Bit Analog-to-Digital Converter (A/D) Register 15-2 is modified as shown to: • Change the bit designations of ADCON<2:0> (PCFG2, PCFG1 and PCFG0) to R/W-0, to match PCFG3 (ADCON<3>) • Remove the notes for ADCON<3:0> The new text appears in bold.
PAGE 4
PIC18F1230/1330 The equations used to calculate the output of the comparator voltage reference are as follows: If CVRR = 1: CVREF = ((CVR3:CVR0)/24) x CVRSRC If CVRR = 0: CVREF = (CVRSRC x 1/4) + (((CVR3:CVR0)/32) x CVRSRC) The comparator reference supply voltage can come from either AVDD or AVSS, or the external VREF+ that is multiplexed with RA4 and AVSS. The voltage source is selected by the CVRSS bit (CVRCON<4>).
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PIC18F1230/1330 FIGURE 17-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ AVDD CVRSS = 1 8R CVRSS = 0 CVR3:CVR0 R CVREN R 16-to-1 MUX R R 16 Steps CVREN = 0 CVREF CVREN = 1 R R R CVRR 8R AVSS © 2008 Microchip Technology Inc.
PAGE 6
PIC18F1230/1330 7. Module: Special Features of the CPU The bit descriptions for Register 19-6, Register 19-13 and Register 19-14 are changed as indicated by the bold and bold and underlined text.
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PIC18F1230/1330 REGISTER 19-13: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F1230/1330 DEVICES R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Read-only bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state bit 7-5 DEV2:DEV0: Device ID bits 000 =PIC18F1230 001 =PIC18F1330 bit 4-0 REV4:REV0: Revision ID bits These bits are used to indicate the device revision.
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PIC18F1230/1330 8. Module: Electrical Characteristics In Table 22-1, the values for the D122 and D133A parameters are changed as indicated by bold text. TABLE 22-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial DC CHARACTERISTICS Param No.
PAGE 9
PIC18F1230/1330 REVISION HISTORY Rev A Document (12/2007) Initial release of this data sheet errata. Includes Data Sheet Clarifications 1 (Oscillator Configurations – PLL), 2 (Flash Program Memory), 3 (EUSART), 4 (A/D), 5 (Comparator), 6 (Comparator Voltage Reference), 7 (Special Features of the CPU) and 8 (Electrical Characteristics). Rev B Document (9/2008) Changes to Data Sheet Clarification 7 (Special Features of the CPU). © 2008 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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