Datasheet

© 2007 Microchip Technology Inc. DS39605F-page 257
PIC18F1220/1320
22.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 22-6: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
TABLE 22-4: EXTERNAL CLOCK TIMING REQUIREMENTS
OSC1
CLKO
Q4 Q1 Q2 Q3 Q4 Q1
1
2
3
3
4
4
Param.
No.
Symbol Characteristic Min Max Units Conditions
1A F
OSC External CLKI Frequency
(1)
DC 40 MHz EC, ECIO (LF and Industrial)
DC 25 MHz EC, ECIO (Extended)
Oscillator Frequency
(1)
DC 4 MHz RC oscillator
DC 1 MHz XT oscillator
DC 25 MHz HS oscillator
1 10 MHz HS + PLL oscillator
DC 33 kHz LP Oscillator mode
1T
OSC External CLKI Period
(1)
25 — ns EC, ECIO (LF and Industrial)
40 — ns EC, ECIO (Extended)
Oscillator Period
(1)
250 — ns RC oscillator
1000 — ns XT oscillator
25
100
—
1000
ns
ns
HS oscillator
HS + PLL oscillator
30 — μs LP oscillator
2TCY Instruction Cycle Time
(1)
100 — ns TCY = 4/FOSC
3 TosL,
TosH
External Clock in (OSC1)
High or Low Time
30 — ns XT oscillator
2.5 — μs LP oscillator
10 — ns HS oscillator
4TosR,
TosF
External Clock in (OSC1)
Rise or Fall Time
— 20 ns XT oscillator
— 50 ns LP oscillator
— 7.5 ns HS oscillator
Note 1: Instruction cycle period (T
CY) equals four times the input oscillator time base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions, with the device executing code. Exceeding these specified limits may result
in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested
to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.