Datasheet
PIC18CXX2
DS39026D-page 90 1999-2013 Microchip Technology Inc.
8.6 Parallel Slave Port
The Parallel Slave Port is implemented on the 40-pin
devices only (PIC18C4X2).
PORTD operates as an 8-bit wide, parallel slave port,
or microprocessor port, when control bit PSPMODE
(TRISE<4>) is set. It is asynchronously readable and
writable by the external world through RD
control input
pin RE0/RD
and WR control input pin RE1/WR.
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD
to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set). The A/D port config-
uration bits PCFG2:PCFG0 (ADCON1<2:0>) must be
set, which will configure pins RE2:RE0 as digital I/O.
A write to the PSP occurs when both the CS
and WR
lines are first detected low. A read from the PSP occurs
when both the CS
and RD lines are first detected low.
The PORTE I/O pins become control inputs for the
microprocessor port when bit PSPMODE (TRISE<4>)
is set. In this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs), and the ADCON1 is configured for digital I/O.
In this mode, the input buffers are TTL.
FIGURE 8-10: PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE
PORT)
FIGURE 8-11: PARALLEL SLAVE PORT WRITE WAVEFORMS
Data Bus
WR LATD
RDx
QD
CK
EN
QD
EN
RD PORTD
pin
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1<7>)
Read
Chip Select
Write
RD
CS
WR
Note: I/O pin has protection diodes to VDD and VSS.
TTL
TTL
TTL
TTL
or
PORTD
RD LATD
Data Latch
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
RD
IBF
OBF
PSPIF
PORTD<7:0>