Datasheet

PIC18CXX2
DS39026D-page 8  1999-2013 Microchip Technology Inc.
FIGURE 1-1: PIC18C2X2 BLOCK DIAGRAM
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKI
OSC2/CLKO
MCLR
VDD, VSS
PORTA
PORTB
PORTC
RA4/T0CKI
RA5/AN4/SS
/LVDIN
RB0/INT0
RB7:RB4
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Brown-out
Reset
Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.
2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction).
3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations
are device dependent.
Addressable
CCP1
Synchronous
Timer0 Timer1 Timer2
Serial Port
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
Timing
Generation
4X PLL
A/D Converter
Precision
Reference
RB1/INT1
Data Latch
Data RAM
Address Latch
Address<12>
12
(2)
BSR
FSR0
FSR1
FSR2
4
12 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
WREG
8
BIT OP
8
8
ALU<8>
8
Address Latch
Program Memory
(up to 2M Bytes)
Data Latch
20
21
21
16
8
8
8
inc/dec logic
21
8
Data Bus<8>
8
Instruction
12
3
ROM Latch
Timer3
CCP2
RB2/INT2
RB3/CCP2
(1)
T1OSI
T1OSO
Bank0, F
PCLATU
PCU
RA6
Voltage
USART
Master
8
Register
Table Latch
Table Pointer <2>
inc/dec
logic
Decode