Datasheet

 1999-2013 Microchip Technology Inc. DS39026D-page 73
PIC18CXX2
REGISTER 7-9: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 (IPR2)
U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1
— — — — BCLIP LVDIP TMR3IP CCP2IP
bit 7 bit 0
bit 7-4 Unimplemented: Read as '0'
bit 3 BCLIP: Bus Collision Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2 LVDIP: Low Voltage Detect Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 CCP2IP: CCP2 Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown