Datasheet

 1999-2013 Microchip Technology Inc. DS39026D-page 47
PIC18CXX2
WDTCON — — — — — — —SWDTE---- ---0 183
RCON IPEN LWRT
—RITO PD POR BOR 0q-1 11qq 53, 56,
74
TMR1H Timer1 Register High Byte xxxx xxxx 97
TMR1L Timer1 Register Low Byte xxxx xxxx 97
T1CON RD16
— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 97
TMR2 Timer2 Register 0000 0000 101
PR2 Timer2 Period Register 1111 1111 102
T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 101
SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 121
SSPADD SSP Address Register in I
2
C Slave Mode. SSP Baud Rate Reload Register in I
2
C Master Mode. 0000 0000 128
SSPSTAT SMP CKE D/A
PSR/WUA BF 0000 0000 116
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 118
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 120
ADRESH A/D Result Register High Byte xxxx xxxx 171,172
ADRESL A/D Result Register Low Byte xxxx xxxx 171,172
ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE
—ADON0000 00-0 165
ADCON1 ADFM ADCS2
— — PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 166
CCPR1H Capture/Compare/PWM Register1 High Byte xxxx xxxx 111, 113
CCPR1L Capture/Compare/PWM Register1 Low Byte xxxx xxxx 111, 113
CCP1CON
— — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 107
CCPR2H Capture/Compare/PWM Register2 High Byte xxxx xxxx 111, 113
CCPR2L Capture/Compare/PWM Register2 Low Byte xxxx xxxx 111, 113
CCP2CON
— — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 107
TMR3H Timer3 Register High Byte xxxx xxxx 103
TMR3L Timer3 Register Low Byte xxxx xxxx 103
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC
TMR3CS TMR3ON 0000 0000 103
SPBRG USART1 Baud Rate Generator 0000 0000 151
RCREG USART1 Receive Register 0000 0000
158, 161,
163
TXREG USART1 Transmit Register 0000 0000
156, 159,
162
TXSTA CSRC TX9 TXEN SYNC
— BRGH TRMT TX9D 0000 -010 149
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 150
TABLE 4-2: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR,
BOR
Details
on page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO oscillator mode only, and read '0' in all other oscillator modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.