Datasheet

PIC18CXX2
DS39026D-page 260  1999-2013 Microchip Technology Inc.
FIGURE 21-20: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 21-19: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 21-21: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 21-20: USART SYNCHRONOUS RECEIVE REQUIREMENTS
121
121
120
122
RC6/TX/CK
RC7/RX/DT
pin
pin
Note: Refer to Figure 21-4 for load conditions.
Param.
No.
Symbol Characteristic Min Max Units Conditions
120 TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock high to data out valid PIC18CXXX — 40 ns
PIC18LCXXX — 100 ns
121 Tckrf Clock out rise time and fall time
(Master mode)
PIC18CXXX — 25 ns
PIC18LCXXX — 50 ns
122 Tdtrf Data out rise time and fall time PIC18CXXX — 25 ns
PIC18LCXXX — 50 ns
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
Note: Refer to Figure 21-4 for load conditions.
Param.
No.
Symbol Characteristic Min Max Units Conditions
125 TdtV2ckl SYNC RCV (MASTER & SLAVE)
Data hold before CK  (DT hold time) 10 — ns
126 TckL2dtl Data hold after CK  (DT hold time) 15 — ns