Datasheet

 1999-2013 Microchip Technology Inc. DS39026D-page 251
PIC18CXX2
FIGURE 21-11: PARALLEL SLAVE PORT TIMING (PIC18C4X2)
TABLE 21-10: PARALLEL SLAVE PORT REQUIREMENTS (PIC18C4X2)
Note: Refer to Figure 21-4 for load conditions.
RE2/CS
RE0/RD
RE1/WR
RD7:RD0
62
63
64
65
Param.
No.
Symbol Characteristic Min Max Units Conditions
62 TdtV2wrH Data in valid before WR
 or CS
(setup time)
20
25
—
—
ns
ns Extended Temp. Range
63 TwrH2dtI WR
 or CS to data–in invalid
(hold time)
PIC18CXXX 20 — ns
PIC18LCXXX 35 — ns
64 TrdL2dtV RD
 and CS to data–out valid —
—
80
90
ns
ns Extended Temp. Range
65 TrdH2dtI RD
 or CS to data–out invalid 10 30 ns
66 TibfINH Inhibit of the IBF flag bit being cleared from
WR
 or CS
—3T
CY