Datasheet

PIC18CXX2
DS39026D-page 218  1999-2013 Microchip Technology Inc.
RETFIE Return from Interrupt
Syntax: [ label ] RETFIE [s]
Operands: s  [0,1]
Operation: (TOS)  PC,
1  GIE/GIEH or PEIE/GIEL,
if s = 1
(WS)  WREG,
(STATUSS)  STATUS,
(BSRS)  BSR,
PCLATU, PCLATH are unchanged.
Status Affected: GIE/GIEH,PEIE/GIEL.
Encoding:
0000 0000 0001 000s
Description: Return from Interrupt. Stack is
popped and Top-of-Stack (TOS) is
loaded into the PC. Interrupts are
enabled by setting either the high
or low priority global interrupt
enable bit. If ‘s’ = 1, the contents of
the shadow registers WS,
STATUSS and BSRS are loaded
into their corresponding registers,
WREG, STATUS and BSR. If
‘s’ = 0, no update of these registers
occurs (default).
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation
No
operation
pop PC from
stack
Set GIEH or
GIEL
No
operation
No
operation
No
operation
No
operation
Example:
RETFIE 1
After Interrupt
PC = TOS
W=WS
BSR = BSRS
STATUS = STATUSS
GIE/GIEH, PEIE/GIEL= 1
RETLW Return Literal to WREG
Syntax: [ label ] RETLW k
Operands: 0  k  255
Operation: k  WREG,
(TOS)  PC,
PCLATU, PCLATH are unchanged
Status Affected: None
Encoding:
0000 1100 kkkk kkkk
Description: WREG is loaded with the eight-bit
literal 'k'. The program counter is
loaded from the top of the stack
(the return address). The high
address latch (PCLATH) remains
unchanged.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal 'k'
Process
Data
pop PC from
stack, Write
to WREG
No
operation
No
operation
No
operation
No
operation
Example:
CALL TABLE ; WREG contains table
; offset value
; WREG now has
; table value
:
TABLE
ADDWF PCL ; WREG = offset
RETLW k0 ; Begin table
RETLW k1 ;
:
:
RETLW kn ; End of table
Before Instruction
WREG = 0x07
After Instruction
WREG = value of kn