Datasheet

PIC18CXX2
DS39026D-page 194  1999-2013 Microchip Technology Inc.
ADDWFC ADD WREG and Carry bit to f
Syntax: [ label ] ADDWFC f [,d [,a]
Operands: 0  f  255
d [0,1]
a [0,1]
Operation: (WREG) + (f) + (C)  dest
Status Affected: N,OV, C, DC, Z
Encoding:
0010 00da ffff ffff
Description: Add WREG, the Carry Flag and data
memory location 'f'. If 'd' is 0, the
result is placed in WREG. If 'd' is 1,
the result is placed in data memory
location 'f'. If ‘a’ is 0, the Access
Bank will be selected. If ‘a’ is 1, the
BSR will not be overridden.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
Process
Data
Write to
destination
Example:
ADDWFC REG, 0, 1
Before Instruction
Carry bit= 1
REG = 0x02
WREG = 0x4D
After Instruction
Carry bit= 0
REG = 0x02
WREG = 0x50
ANDLW AND literal with WREG
Syntax: [ label ] ANDLW k
Operands: 0  k  255
Operation: (WREG) .AND. k  WREG
Status Affected: N,Z
Encoding:
0000 1011 kkkk kkkk
Description: The contents of WREG are ANDed
with the 8-bit literal 'k'. The result is
placed in WREG.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
'k'
Process
Data
Write to
WREG
Example:
ANDLW 0x5F
Before Instruction
WREG = 0xA3
After Instruction
WREG = 0x03