Datasheet

PIC18CXX2
DS39026D-page 166  1999-2013 Microchip Technology Inc.
REGISTER 16-2: ADCON1 REGISTER
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM ADCS2
— — PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified. Six (6) Most Significant bits of ADRESH are read as ’0’.
0 = Left justified. Six (6) Least Significant bits of ADRESL are read as ’0’.
bit 6 ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in bold)
bit 5-4 Unimplemented: Read as '0'
bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Note: On any device RESET, the port pins that are multiplexed with analog functions (ANx) are
forced to be an analog input.
ADCON1
<ADCS2>
ADCON0
<ADCS1:ADCS0>
Clock Conversion
0 00 F
OSC/2
0 01 F
OSC/8
0 10 F
OSC/32
0 11 F
RC (clock derived from the internal A/D RC oscillator)
1 00 F
OSC/4
1 01 F
OSC/16
1 10 F
OSC/64
1 11 F
RC (clock derived from the internal A/D RC oscillator)
A = Analog input D = Digital I/O
C/R = # of analog input channels/# of A/D voltage references
PCFG AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 V
REF+VREF- C / R
0000 A A A A A A A A V
DD VSS 8 / 0
0001 A A A A V
REF+A A AAN3VSS 7 / 1
0010 D D D A A A A A VDD VSS 5 / 0
0011 D D D A VREF+A A AAN3VSS 4 / 1
0100 D D D D A D A A V
DD VSS 3 / 0
0101 D D D D VREF+D A AAN3VSS 2 / 1
011x D D D D D D D D — — 0 / 0
1000 A A A A V
REF+VREF- A A AN3 AN2 6 / 2
1001 D D A A A A A A V
DD VSS 6 / 0
1010 D D A A VREF+A A AAN3VSS 5 / 1
1011 D D A A V
REF+VREF- A A AN3 AN2 4 / 2
1100 D D D A V
REF+VREF- A A AN3 AN2 3 / 2
1101 D D D D VREF+VREF- A A AN3 AN2 2 / 2
1110 D D D D D D D A V
DD VSS 1 / 0
1111 D D D D V
REF+VREF- D A AN3 AN2 1 / 2