Datasheet

PIC18CXX2
DS39026D-page 136  1999-2013 Microchip Technology Inc.
14.4.5 BAUD RATE GENERATOR
In I
2
C Master mode, the reload value for the BRG is
located in the lower 7 bits of the SSPADD register
(Figure 14-14). When the BRG is loaded with this
value, the BRG counts down to 0 and stops until
another reload has taken place. The BRG count is dec-
remented twice per instruction cycle (T
CY) on the Q2
and Q4 clocks. In I
2
C Master mode, the BRG is
reloaded automatically. If Clock Arbitration is taking
place, for instance, the BRG will be reloaded when the
SCL pin is sampled high (Figure 14-15).
FIGURE 14-14: BAUD RATE GENERATOR BLOCK DIAGRAM
FIGURE 14-15: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SSPM3:SSPM0
BRG Down Counter
CLKOUT
F
OSC/4
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control
Reload
SDA
SCL
SCL de-asserted but slave holds
DX-1DX
BRG
SCL is sampled high, reload takes
place and BRG starts its count.
03h 02h 01h 00h (hold off) 03h 02h
Reload
BRG
Value
SCL low (clock arbitration)
SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles