Datasheet

PIC18CXX2
DS39026D-page 134  1999-2013 Microchip Technology Inc.
14.4.4 I
2
C MASTER MODE SUPPORT
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. Once Master mode is enabled, the user
has six options.
1. Assert a START condition on SDA and SCL.
2. Assert a Repeated START condition on SDA
and SCL.
3. Write to the SSPBUF register initiating transmis-
sion of data/address.
4. Generate a STOP condition on SDA and SCL.
5. Configure the I
2
C port to receive data.
6. Generate an Acknowledge condition at the end
of a received byte of data.
FIGURE 14-13: MSSP BLOCK DIAGRAM (I
2
C MASTER MODE)
Note: The MSSP module, when configured in I
2
C
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
imitate transmission, before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
Read Write
SSPSR
START bit, STOP bit,
START bit Detect
SSPBUF
Internal
Data Bus
Set/Reset, S, P, WCOL (SSPSTAT)
Shift
Clock
MSb
LSb
SDA
Acknowledge
Generate
STOP bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
SCL
SCL in
Bus Collision
SDA in
Receive Enable
Clock Cntl
Clock Arbitrate/WCOL Detect
(hold off clock source)
SSPADD<6:0>
Baud
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
Rate
Generator
SSPM3:SSPM0